Semiconductor Package Stud Bump Interconnects
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Solution Overview
Problem
The manufacturing process of semiconductor packages is complicated and costly due to the need for conductive vias formed by drilling and plating, which increases difficulty and expense, and the formation of top and bottom circuitries through seed layer formation and pattern-plating.
Innovation Solution
A semiconductor package design that incorporates stud bumps as conductive interconnectors, formed by wire bonding, to connect top and bottom circuitries, and uses a metal sheet that remains partially intact during processing to simplify the formation of circuitries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are formed by drilling and plating, then electrical connection between top and bottom circuitry is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the complex drilling and plating operations from the manufacturing process by replacing them with wire bonding technology. The stud bumps are formed through wire bonding directly between the top and bottom circuitries, eliminating the need for conductive vias and their associated complex steps.
Solution Approach 2:
The patent replaces the mechanical drilling and electrochemical plating system with a wire bonding system. Instead of mechanically drilling holes and chemically depositing metal, the invention uses controlled wire placement and bonding to create electrical connections, substituting a simpler mechanical process for complex mechanical-chemical processes.
2Reliability
If seed layer formation and pattern-plating are used to create circuitries, then conductive pathways are formed, but manufacturing cost and difficulty increase
Solution Approach 1:
The patent removes the seed layer formation and pattern-plating steps from the manufacturing process. Circuitries are formed through direct wire bonding operations that create conductive pathways without requiring preliminary seed layers or complex pattern-plating procedures.
Solution Approach 2:
The patent substitutes the electrochemical deposition system (seed layer and pattern-plating) with a direct wire bonding system. The wire bonding process directly creates the conductive circuitries through controlled wire placement and bonding, eliminating the need for electrochemical deposition processes.
3Device complexity
If wire bonding is used to form stud bumps, then manufacturing complexity is reduced, but connection reliability must be maintained
Solution Approach 1:
The patent optimizes wire bonding parameters such as bonding pressure, temperature, and current to ensure reliable connections. By carefully controlling these parameters, the wire bonding process achieves connection reliability comparable to or exceeding traditional conductive via methods while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and cost by eliminating the need for drilling and plating, while ensuring secure connections and improved surface conditions for stud bumps, enhancing the reliability and efficiency of the semiconductor package assembly.
Implementation Method 1
stud bumps as conductive interconnectors, formed by wire bonding
Implementation Method 2
uses a metal sheet that remains partially intact during processing to simplify the formation of circuitries
Data Source
AI summary
A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.