Semiconductor Sub-Assembly Embedded Signal Pads
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Solution Overview
Problem
Semiconductor power modules face challenges in reducing thermal resistance and achieving a smaller size due to the limitations of wire bonding connections and the mechanical strength of signal electrodes, particularly in double-sided cooling packages.
Innovation Solution
A semiconductor sub-assembly with embedded substrates and extension signal electrode pads allows for connection without wire bonding, reducing thermal resistance and module thickness by using metal-plated connections and omitting spacers, enabling improved insulation and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding connection is used for connecting signal terminals, then mechanical strength and reliability are improved, but thermal resistance increases and module size cannot be reduced
Solution Approach 1:
The patent removes the wire bonding connection and spacer from the module structure, extracting the harmful thermal resistance and insulating space requirements. The signal electrode pad is directly connected to the external terminal without intermediate wire bonding components, eliminating the thermal barrier and space occupation caused by wire bonding.
Solution Approach 2:
The patent merges the signal electrode pad and external terminal connection into a direct integrated structure. The signal electrode pad on the chip surface is directly connected to the external terminal through the module structure without wire bonding, combining multiple functions into a unified thermal and electrical conduction path.
2Reliability
If wire bonding connection is used, then signal terminal connection is achieved, but assembly operations become complex and time-consuming
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the assembly operations. By removing the wire bonding connection requirement, the complex multi-step assembly process is simplified into a direct integration approach, significantly reducing manufacturing complexity and time.
3Power
If chip size is reduced to improve performance, then signal electrode pad size decreases, but wire bonding mechanical strength becomes insufficient
Solution Approach 1:
The patent removes the wire bonding connection that becomes mechanically weak with smaller chip sizes. By eliminating wire bonding entirely and using direct connection through the module structure, the mechanical strength limitation is overcome while maintaining the ability to use smaller, high-performance chips.
4Reliability
If insulating space is secured for wire bonding, then wire bonding connection is possible, but module thickness increases
Solution Approach 1:
The patent extracts and removes the insulating space requirement from the module design. By eliminating wire bonding and its associated insulation needs, the module thickness is reduced while maintaining reliable electrical connections through the direct integrated structure.
Solution Approach 2:
The patent transitions from a three-dimensional wire bonding approach requiring vertical insulating space to a planar integrated connection approach. The signal electrode pad is directly connected to external terminals through the module structure in the same plane, eliminating the need for vertical insulation space and reducing overall module thickness.
Data Source
AI summary
A semiconductor sub-assembly and a semiconductor power module capable of having the reduced thickness of a chip and reduced thermal resistance are provided. The semiconductor sub-assembly includes a single or a plurality of semiconductor chips having a first electrode that is formed on the lower surface thereof, a second electrode that is formed on the upper surface thereof, and a plurality of chip-side signal electrode pads that are formed at one end of the upper surface thereof. The semiconductor chip is embedded in the embedded structure and a plurality of extension signal electrode pads are connected to each of the chip-side signal electrode pads. The extension signal electrode pad is formed on the embedded substrate in a size greater than the chip-side signal electrode pad when viewed on the plane.