Semiconductor Device Sub-Collector Layer Segmentation
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Solution Overview
Problem
The existing semiconductor device with a 300 nm-thick GaAs sub-collector layer increases collector resistance in HBT and on-resistance in HFET, failing to satisfy both characteristic advantages simultaneously.
Innovation Solution
A semiconductor device structure with a sub-collector layer having an external and internal sub-collector region, where the mesa-shaped collector part includes the base, emitter, and internal sub-collector layer, and the cap layer includes the external sub-collector region, allowing for reduced on-resistance in both HBT and HFET by sharing a single semiconductor layer and minimizing mask usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single shared GaAs layer is used for both HBT sub-collector and HFET cap layer, then the number of masks and manufacturing steps is reduced, but the on-resistance of both devices increases due to the trade-off in thickness optimization
Solution Approach 1:
The patent segments the shared GaAs layer into external and internal sub-collector regions with different functional optimizations. This allows the single layer to serve dual purposes with region-specific performance characteristics, maintaining manufacturing simplicity while improving device performance by allowing each region to be optimized for its specific device type.
Solution Approach 2:
The shared GaAs layer is designed to perform multiple functions simultaneously: serving as the sub-collector for the HBT in the external region and as the cap layer for the HFET in the internal region. This multi-functionality maintains the manufacturing advantages of a single layer while the regional segmentation enables performance optimization for both device types.
Data Source
AI summary
A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.