Semiconductor Substrate Sawing with Amorphous Region and Partition Structure
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Solution Overview
Problem
The existing methods for sawing substrates to separate semiconductor devices often result in damage to the devices and reduced manufacturing yield due to poor sawing processes.
Innovation Solution
A substrate with a crystalline semiconductor layer, a dielectric layer, and a partition structure is used, where an amorphous region is formed in the scribe lane and a grinding process is applied to separate the devices, with the partition structure having a different strength than the dielectric layer to control crack propagation and prevent damage to integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional sawing process is used to separate semiconductor devices, then the substrate can be divided into individual devices, but the devices may become damaged and manufacturing yield is reduced
Solution Approach 1:
The substrate is divided into device regions and scribe lane regions, with partition structures creating isolated zones. This segmentation allows the sawing process to occur in controlled sections rather than across the entire substrate, reducing the risk of damage to active device areas while maintaining high manufacturing yield through systematic separation of individual devices
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the crystalline semiconductor layer and the sawing process. This dielectric layer acts as a protective mediator that absorbs or deflects mechanical stresses during sawing, preventing direct transmission of damaging forces to the semiconductor devices while still allowing effective substrate division
2Productivity
If the sawing process is aggressive enough to separate devices quickly, then productivity increases, but device damage and yield reduction worsen
Solution Approach 1:
Different regions of the substrate are assigned different functional qualities: device regions are protected with higher precision requirements while scribe lane regions are designed for efficient separation. The partition structures create localized zones with optimized mechanical properties that enable aggressive sawing in scribe lanes without compromising the precision and integrity of device regions, thus maintaining both high productivity and manufacturing precision
Solution Approach 2:
Partition structures are formed in advance during substrate fabrication, creating pre-defined separation zones before the sawing process begins. This preliminary action prepares the substrate with built-in separation pathways that guide the sawing process, allowing for faster and more precise device separation without the need for aggressive or imprecise sawing operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively separates semiconductor devices without damaging them, increases the number of device regions by reducing kerf width, and enhances manufacturing yield by preventing crack propagation into device regions.
Implementation Method 1
An amorphous region may be formed in the crystalline semiconductor layer and a grinding process may be performed on the crystalline semiconductor layer after the amorphous region is formed. The partition structure may have a different strength from the dielectric layer to control crack propagation and prevent damage to integrated circuits.
Implementation Method 2
The partition structure may have a different strength from the dielectric layer to control crack propagation and prevent damage to integrated circuits.
Data Source
AI summary
A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.