Semiconductor Substrate Bonding via Low-Temperature Direct Join

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Solution Overview

Problem

The manufacturing of miniaturized semiconductor devices, such as MEMS packages, faces challenges with high temperature and compressive force during eutectic bonding, leading to thermal internal stress, cracks, and damage to electrical interconnects, which affects the reliability and performance of the devices.

Innovation Solution

A semiconductor structure is developed where substrates are bonded using directly bonded conductive structures and dielectric layers, allowing for bonding under low temperatures (less than 250°C) without the application of compressive force, thereby preventing damage and ensuring reliable integration of devices like accelerometers and gyroscopes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If eutectic bonding is used to bond substrates, then strong bonding strength is achieved, but high temperature and compressive force cause thermal internal stress, cracks, and damage to electrical interconnects

Engineering Contradiction:
Improvebonding strengthVSAvoidthermal internal stress, cracks, and damage to electrical interconnects
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The patent changes the bonding parameters from high temperature (eutectic bonding) to low temperature (less than 250°C), and from compressive force to tensile force. This parameter transformation allows achieving strong bonding strength while avoiding thermal internal stress, cracks, and damage to electrical interconnects that occur with conventional eutectic bonding

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical compression-based eutectic bonding system with a tension-based bonding system. By applying tensile force instead of compressive force during bonding, the method achieves strong substrate bonding without causing thermal internal stress or mechanical damage to sensitive electrical interconnects

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Volume of moving object

If miniaturization is pursued to reduce device size, then geometric size decreases, but manufacturing complexity increases leading to high yield loss and poor reliability

Engineering Contradiction:
Improvedevice sizeVSAvoidelectrical interconnection reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent changes the bonding temperature parameter to low temperature (less than 250°C), which prevents thermal damage to miniaturized electrical interconnects and maintains their reliability while allowing continued device miniaturization

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies low temperature and tensile force bonding as a protective measure before electrical interconnects can be damaged by high temperature or compressive force, thereby cushioning against potential reliability issues in miniaturized devices

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability and performance of semiconductor structures by avoiding high-temperature and high-force-induced damage, allowing for the formation of complex MEMS devices with improved yield and reduced manufacturing costs.

Implementation Method 1

bonding under low temperatures (less than 250°C) without the application of compressive force

Methodology Applied
Scientific EffectDirect bonding: Diffusion Welding

Data Source

PatentUS10781098B2Method of manufacturing semiconductor structure
Publication Date: 2020.09.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10781098B2 patent drawing
  • US10781098B2 patent drawing
  • US10781098B2 patent drawing

AI summary

A method of manufacturing a semiconductor structure includes receiving a first substrate including a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; receiving a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; and bonding the first conductive structure with the second conductive structure.