Semiconductor Substrate Bonding Interface Impurity Profile Control

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Solution Overview

Problem

Non-ohmic conduction occurs at the bonded interface between semiconductor substrates, affecting device characteristics in devices with current pathways across the interface.

Innovation Solution

A method involving impurity implantation and heat treatment to narrow the in-depth concentration profile of impurities at the bonded interface, preventing non-ohmic conduction by controlling the distribution and concentration of impurities in the semiconductor layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If direct bonding is performed between semiconductor substrates, then substrate integration is achieved, but non-ohmic conduction occurs at the bonded interface

Engineering Contradiction:
Improvesubstrate integrationVSAvoidelectrical conduction at interface
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing impurity implantation into the semiconductor layers before the bonding step. This pre-treatment ensures that when the substrates are bonded, the impurity regions are already positioned to facilitate carrier generation and eliminate non-ohmic conduction at the interface, rather than attempting to fix the problem after bonding occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by controlling the concentration and depth distribution of impurities through implantation. By adjusting impurity concentration parameters in the semiconductor layers adjacent to the bonding interface, the electrical characteristics are modified to ensure ohmic conduction, transforming the electrical state of the interface region.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If impurity concentration is increased at the bonded interface, then carrier generation is enhanced, but non-ohmic conduction may occur due to excessive impurity width

Engineering Contradiction:
Improvecarrier generationVSAvoidimpurity concentration profile
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a localized impurity region with specific concentration characteristics adjacent to the bonding interface. The impurity is implanted to achieve a concentrated distribution pattern that provides sufficient carrier generation locally at the interface while maintaining controlled width parameters, rather than uniformly distributing impurities throughout the entire substrate.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent replaces mechanical/physical bonding processes with a chemically-influenced bonding approach by using impurity implantation to modify the electrical properties at the bonding interface. The impurity-induced carrier generation substitutes for purely mechanical contact resistance reduction, enabling ohmic conduction through electrical property modification rather than just physical bonding pressure.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves electrical characteristics of semiconductor substrates by preventing non-ohmic conduction and enhancing carrier generation and tunneling across the bonded interface.

Implementation Method 1

An irradiating step of irradiating the bonded substrate with neutral atoms is executed. The irradiating step causes the first impurity to be implanted into the vicinity of the surface of the first semiconductor layer and the vicinity of the surface of the second semiconductor layer.

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

A heat treating step of applying heat treatment to the bonded substrate is executed. The irradiating step causes the first impurity to be implanted into the vicinity of the surface of the first semiconductor layer and the vicinity of the surface of the second semiconductor layer. This causes the first impurity thus implanted to be present in the vicinity of the bonded interface between the first and second semiconductor layers

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Data Source

PatentEP3168862B1Semiconductor substrate and semiconductor substrate production method
Publication Date: 2022.07.06 SICOXS
  • EP3168862B1 patent drawingFigure 1
  • EP3168862B1 patent drawingFigure 2
  • EP3168862B1 patent drawingFigure 3

AI summary

A technology disclosed herein relates to a method for manufacturing a semiconductor substrate and the like that make it possible to improve the electrical characteristics of a semiconductor substrate including first and second semiconductor layers that are in contact with each other. The method may comprise an irradiating step of irradiating a surface of the first semiconductor layer with one or more types of first impurity in a vacuum and irradiating a surface of the second semiconductor layer with the one or more types of first impurity in the vacuum. The method may comprise a bonding step of bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum in which the irradiating step was executed and thereby producing a semiconductor substrate having a bonded interface. The method may comprise a heat treating step of applying heat treatment to the semiconductor substrate produced in the bonding step. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treating step than before the execution of the heat treating step.