Semiconductor Substrate With Embedded Cavity For Height Reduction
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Solution Overview
Problem
Semiconductor packages are too large due to the size of their electrical components, making them unfit for certain devices, and existing technologies have not effectively minimized their size without compromising structural integrity or electrical performance.
Innovation Solution
A semiconductor package design featuring a substrate with electronically conducting vias embedded in dielectric material, where one electrical component is partially embedded in a cavity formed within the substrate, reducing the overall z-directional height and allowing for the incorporation of larger components, while using sidewall conductive material for connections instead of the bottom surface, facilitating easier detection and repair of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical components are made larger to improve functionality, then electrical performance is improved, but the overall package size increases
Solution Approach 1:
The patent transitions from planar component placement to three-dimensional cavity embedding. Electrical components are positioned within cavities formed in the substrate, utilizing the z-directional dimension to reduce the overall package footprint while accommodating larger components with improved electrical performance
Solution Approach 2:
The patent embeds electrical components within cavities formed in the substrate, creating a nested structure where components are housed inside the substrate volume rather than occupying additional planar space. This nesting approach allows larger components to be accommodated without increasing the overall package footprint
2Length of stationary object
If components are embedded deeper in the substrate, then package height is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms cavities in the substrate before placing electrical components, allowing for controlled depth and positioning. This preliminary cavity formation simplifies the subsequent component embedding process and enables precise control over the embedded depth, thereby managing manufacturing complexity while achieving reduced package height
Solution Approach 2:
The patent divides the substrate into regions with and without cavities, allowing selective embedding of components. This segmentation enables optimized manufacturing processes where cavities are formed only in specific locations, reducing overall manufacturing complexity compared to complete substrate transformation
3Ease of manufacture
If conventional planar component placement is used, then manufacturing is simpler, but package size becomes too large
Solution Approach 1:
The patent moves from two-dimensional planar placement to three-dimensional cavity embedding, utilizing the vertical dimension within the substrate to accommodate components. This dimensional transition reduces the planar footprint and overall package size while maintaining manufacturing feasibility through standardized cavity formation processes
Data Source
AI summary
Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.