Semiconductor Package With Substrate Cavity And Internal Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
A semiconductor device design comprising a substrate with a cavity, a device stack, internal interconnects, and an encapsulant that covers the substrate and fills the cavity, providing protection and electrical coupling while optimizing size and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packages are used, then manufacturing is simpler, but package size becomes too large
Solution Approach 1:
The patent implements nesting by placing the device stack inside a cavity formed within the substrate. The cavity acts as a container that holds the stacked electronic devices, allowing the package to occupy less external volume while maintaining all necessary functional components. This nested configuration directly reduces the overall package size compared to conventional flat-pack arrangements.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical stack configuration. By stacking electronic devices vertically within the substrate cavity and using vertical interconnects, the design exploits the third dimension (height) to increase component density, thereby reducing the footprint and overall package volume.
2Ease of manufacture
If conventional semiconductor packages are used, then manufacturing process is traditional, but cost increases
Solution Approach 1:
The cavity is pre-formed within the substrate before the device stack is assembled and installed. This preliminary structuring of the substrate provides a ready-made housing that guides subsequent assembly steps, simplifies alignment, and ensures proper positioning of the device stack, thereby maintaining ease of manufacture while improving reliability through better structural integration.
Solution Approach 2:
The patent merges multiple functions into integrated structures: the substrate serves both as a mechanical support and as a housing (via the cavity) for the device stack; the encapsulant simultaneously protects the devices and provides electrical isolation; and the interconnect structure integrates both electrical connectivity and structural support functions, reducing the need for separate components and simplifying manufacturing.
3Reliability
If conventional semiconductor packages are used, then design is traditional, but performance decreases
Solution Approach 1:
The nested cavity structure provides enhanced protection for the device stack, improving reliability by shielding components from environmental factors and mechanical stress. The encapsulant further nested within the cavity adds another layer of protection, creating a robust multi-layer protective system that enhances device reliability.
Solution Approach 2:
The vertical stacking architecture improves performance by reducing signal path lengths between stacked devices, enabling faster signal transmission and lower power consumption. The three-dimensional interconnect structure provides multiple parallel pathways for electrical signals, increasing bandwidth and improving overall package performance despite the increased design complexity.
Data Source
AI summary
In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.