Semiconductor Substrate Channel Structure for Stress and Residue Relief

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Solution Overview

Problem

Semiconductor devices face challenges with stress and residue accumulation due to the absence of channels at the bottom of the substrate, leading to potential mechanical stress and residue accumulation issues during manufacturing processes.

Innovation Solution

Incorporating channels at the bottom of the semiconductor device substrate to facilitate fluid discharge and reduce mechanical stress, while also serving as outlets for process residues, thereby improving device performance and reducing stress-related issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If channels are added at the bottom of the substrate, then mechanical stress is reduced and residue discharge is improved, but device complexity increases

Engineering Contradiction:
Improvemechanical stress reductionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate is segmented by introducing channels that divide the bottom surface into multiple regions. These channels create separate pathways for stress relief and residue discharge, effectively segmenting the monolithic substrate structure into functional zones that independently address mechanical and chemical concerns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The channels act as intermediary structures that mediate between the internal cavity environment and the external atmosphere. They provide a controlled interface for stress distribution and residue egress, serving as a buffer zone that protects the main device structure while facilitating necessary exchanges with the environment.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If channels are added at the bottom of the substrate, then residue accumulation is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improveresidue accumulationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The channels are formed in the substrate before the cavity is sealed, establishing permanent drainage pathways in advance. This preliminary structuring ensures that residue can escape during subsequent processing steps without requiring additional active management or post-processing modifications.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The channel structure enables the device to self-drain residues through gravity and pressure differential alone, without requiring external pumping or active clearance mechanisms. The geometry of the channels is designed to passively facilitate fluid flow and particle egress based on natural physical forces.

Inventive Principle:
Principle #25Self-service

3Productivity

If channels are incorporated into the substrate, then fluid discharge efficiency is improved, but structural complexity increases

Engineering Contradiction:
Improvefluid discharge efficiencyVSAvoidsubstrate structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The channel network introduces a third-dimensional pathway system within the substrate thickness, transforming the two-dimensional residue accumulation problem into a three-dimensional flow path. This vertical integration of drainage channels allows efficient fluid discharge without expanding the planar footprint of the device.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11769716B2Semiconductor device and methods of forming the same
Publication Date: 2023.09.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11769716B2 patent drawing
  • US11769716B2 patent drawing
  • US11769716B2 patent drawing

AI summary

A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.