Semiconductor Substrate CTE Matching via Thermal Spray
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Solution Overview
Problem
The existing semiconductor substrate fabrication methods face challenges due to Coefficient of Thermal Expansion (CTE) mismatches between epitaxial layers and base substrates, leading to issues such as strain, cracking, and increased complexity in device fabrication, particularly in the formation of high power and photonic devices like LEDs and laser diodes.
Innovation Solution
The method involves forming a weakened zone in a donor structure to create a transfer layer with a substrate layer that closely matches the CTE of the epitaxial layer, providing structural support and enabling the separation of the transfer layer from the donor structure to form a composite substrate with a base substrate layer that matches the CTE of the epitaxial layer, thereby reducing strain and facilitating efficient device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an epitaxial layer is formed on a base substrate with mismatched CTE, then the device can be fabricated, but strain and cracking occur in the semiconductor layers
Solution Approach 1:
The patent introduces an intermediary layer between the base substrate and the epitaxial layer. This intermediary layer has a CTE that is closely matched to the epitaxial layer, serving as a mediator that eliminates the harmful CTE mismatch effects while still allowing the device fabrication process to proceed
Solution Approach 2:
The patent creates a composite substrate structure consisting of a base substrate and an overlying intermediary layer. This composite material approach allows combining the mechanical support function of the base substrate with the CTE-matching function of the intermediary layer, resolving the contradiction between ease of manufacture and structural integrity
2Strength
If a thick base substrate is used to provide structural support, then handling is facilitated, but CTE mismatch strain is increased
Solution Approach 1:
The patent segments the substrate function into two distinct layers: a thick base substrate for structural support and handling, and a thin intermediary layer for CTE matching. This segmentation allows each layer to optimize its specific function without compromising the other, resolving the contradiction between strength and strain reduction
3Ease of manufacture
If conventional substrate fabrication is used, then manufacturing is simple, but device complexity increases due to strain management requirements
Solution Approach 1:
The patent performs preliminary action by forming the intermediary layer during the substrate fabrication process itself, before the epitaxial growth and device fabrication steps. This preliminary CTE-matching layer is built in advance, eliminating the need for complex strain management techniques during subsequent device fabrication steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces strain and cracking in semiconductor layers, simplifies device fabrication, and enhances the structural integrity and performance of high power and photonic devices by ensuring a close match in thermal expansion coefficients between the substrate and epitaxial layers.
Implementation Method 1
forming a first substrate layer over a surface of a first semiconductor layer; forming a second substrate layer over a surface of the first substrate layer opposite the first semiconductor layer
Data Source
AI summary
Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.


