Semiconductor Substrate Layout for Blocking Electron Injection
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Solution Overview
Problem
In semiconductor devices with power switching elements, the injection of electrons from the drain region into the substrate can degrade performance by affecting adjacent transistors, particularly when the drain region has a negative potential, leading to potential issues with minority carrier injection and diffusion in p-type semiconductor regions.
Innovation Solution
The semiconductor device design includes a n-type buried layer, n-type semiconductor region, and n-type substrate region under the p-type semiconductor region, with a potential gradient that directs injected electrons from the drain region to be discharged through the n-type region without entering the p-type region, ensuring they are routed to a plug for extraction, thus preventing adverse effects on adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between element regions is increased to prevent electron injection into adjacent transistors, then the performance of adjacent transistors is maintained, but the device area increases
Solution Approach 1:
A fifth semiconductor region of the first conductivity type is introduced as an intermediary between the third semiconductor region (containing first element region) and the fourth semiconductor region (containing second element region). This intermediary region acts as a buffer that prevents direct electron injection from the drain region into adjacent transistors, thereby maintaining transistor performance without requiring increased spacing between element regions.
Solution Approach 2:
The solution transitions from addressing the problem in the horizontal plane (increasing distance between element regions) to addressing it in the vertical dimension (introducing the fifth semiconductor region that reaches from the buried layer to the upper surface). This vertical structure effectively blocks electron injection paths without consuming additional lateral area.
2Object-affected harmful factors
If a complex substrate structure with multiple semiconductor regions is implemented to control electron injection, then electron injection into p-type regions is prevented, but the substrate structure complexity increases
Solution Approach 1:
The fifth semiconductor region is formed with the same conductivity type (first conductivity type) as the substrate region and the first and second semiconductor regions. This homogeneity in conductivity type simplifies the overall substrate structure by using regions of uniform electrical characteristics, while still achieving the functional goal of preventing electron injection into p-type regions through the coordinated arrangement of these homogeneous regions.
3Object-affected harmful factors
If the fifth semiconductor region reaches from the buried layer to the upper surface, then electron injection is effectively blocked, but the manufacturing process complexity increases
Solution Approach 1:
The fifth semiconductor region is formed in advance during the substrate preparation phase, before the transistors are fully fabricated. By pre-forming this protective region that extends from the buried layer to the upper surface, the structure is ready to block electron injection paths before devices are assembled, simplifying the overall manufacturing process compared to adding protective structures after transistor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents electron injection into p-type semiconductor regions, maintaining the performance of adjacent transistors and allowing for miniaturization of the semiconductor device without increasing the distance between element regions.
Implementation Method 1
with a potential gradient that directs injected electrons from the drain region to be discharged through the n-type region
Data Source
AI summary
A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.