Semiconductor Substrate End-Portion Design for Conductor Loss Reduction
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Solution Overview
Problem
Semiconductor devices experience conductor loss due to the resistance of the semiconductor substrate when a voltage is applied, particularly because the substrate's structure can create electric fields between lands and base electrodes, and existing designs face challenges in surface mounting and stress concentration during heat treatment.
Innovation Solution
The semiconductor device features a substrate with specific end-portion regions where the circuit layer is not provided, exposing portions of the substrate to reduce the volume through which electric lines of force pass, thereby minimizing conductor loss. This design includes first and second outer electrodes extended to the surface, with the substrate having chamfered edges to decrease resistance-induced losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate is a conductor and voltage is applied, then electrical connection is achieved, but conductor loss is caused by the substrate's resistance to the electric field
Solution Approach 1:
The patent extracts the harmful conductive substrate material from the region where electric fields pass through it. By replacing the conductor substrate with an insulator substrate in the electric field path, the source of conductor loss is removed while maintaining electrical connections through alternative means (electrodes on the insulator substrate).
Solution Approach 2:
The patent introduces an insulator substrate as an intermediary material between the electrodes, replacing the direct conductive path through the substrate. This intermediary prevents the harmful interaction between the electric field and the conductive substrate, eliminating conductor loss while still enabling electrical functionality through the electrode structures.
2Reliability
If the circuit layer is provided over the entire substrate surface, then electrical functionality is maximized, but conductor loss increases due to larger volume through which electric lines of force pass
Solution Approach 1:
The patent applies local quality by providing the circuit layer only in specific regions where it is needed for electrical functionality, rather than covering the entire substrate. This localized approach reduces the volume through which electric lines of force pass through the conductive substrate, thereby reducing conductor loss while maintaining necessary electrical functions.
Solution Approach 2:
The patent segments the substrate into regions with circuit layers and regions without circuit layers. By dividing the substrate surface into functional and non-functional areas, the electric field path through the conductive substrate is minimized, reducing conductor loss while preserving electrical functionality in the segmented circuit regions.
3Strength
If step portions are added to the substrate to prevent stress concentration, then mechanical strength is improved, but surface mounting becomes difficult due to non-planar surfaces
Solution Approach 1:
The patent resolves the contradiction by moving the stress management function to another dimension - using an insulator substrate that inherently prevents stress concentration through its material properties rather than geometric features. This maintains a planar surface for easy mounting while addressing stress resistance through the choice of insulating material that does not concentrate stresses during heat treatment.
Data Source
AI summary
A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.