Semiconductor Substrate Layout for Low Parasitic Inductance

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Solution Overview

Problem

Parasitic inductance between substrates in semiconductor devices and light emitting devices, such as those using surface-emitting lasers, affects their operation and accuracy in distance measurement applications.

Innovation Solution

A semiconductor device configuration with a first substrate and a second substrate, where the second electrode extends in a direction parallel to the first electrode, and a wiring with a transistor and capacitor connected to it, reduces parasitic inductance by aligning current paths to minimize magnetic field interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple substrates are combined to manufacture semiconductor devices, then device functionality is improved, but parasitic inductance between substrates increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidparasitic inductance
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent positions the second electrode and wiring to run parallel and close to each other, converting the potentially harmful magnetic field interaction into a beneficial cancellation effect. The adjacent current paths generate opposing magnetic fields that neutralize each other, transforming the harmful parasitic inductance into a design feature that reduces overall inductance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the geometric parameters of the electrode and wiring arrangement by extending the second electrode in the first direction and positioning the wiring to run parallel to it. This parameter optimization minimizes the loop area and maximizes magnetic field cancellation, thereby reducing parasitic inductance while maintaining electrical connectivity.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If the second electrode extends parallel to the first direction and wiring extends parallel to the second direction, then parasitic inductance is reduced, but device layout complexity increases

Engineering Contradiction:
Improveparasitic inductanceVSAvoidlayout complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The second electrode serves multiple functions: it provides electrical connection between substrates and simultaneously acts as a current path configured for magnetic field cancellation. The wiring also serves dual purposes of electrical connection and inductance reduction. This multi-functionality reduces the need for additional dedicated inductance-reduction structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical connection function with the inductance reduction function by configuring the second electrode and wiring to run parallel and adjacent to each other. This combination eliminates the need for separate inductance-reduction structures, simplifying the overall device layout while achieving both connectivity and low inductance.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces parasitic inductance, improving the operational efficiency and accuracy of semiconductor devices and distance measuring devices by aligning current paths to cancel out magnetic fields, thereby enhancing performance and reducing errors in distance measurement.

Implementation Method 1

by bringing the current path in the second electrode and the current path in the wiring close to each other, the parasitic inductance between the first substrate and the second substrate can be reduced

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS20240413077A1Semiconductor device and distance measuring device
Publication Date: 2024.12.12 SONY SEMICON SOLUTIONS CORP
  • US20240413077A1 patent drawing
  • US20240413077A1 patent drawing
  • US20240413077A1 patent drawing

AI summary

Provided are a semiconductor device and a distance measuring device capable of reducing parasitic inductance between a plurality of substrates. The semiconductor device of the present disclosure includes: a first substrate including a semiconductor element, a first electrode provided on the semiconductor element, and a second electrode extending in a first direction in plan view; a second substrate including a wiring extending in a second direction parallel to the first direction in plan view, a transistor electrically connected to the wiring, and a capacitor electrically connected to the wiring; a first connection portion electrically connecting the first electrode and the second substrate; and a second connection portion electrically connecting the second electrode and the second substrate.