Semiconductor Substrate Surface Annealing for Leakage Reduction
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Solution Overview
Problem
Current semiconductor fabrication technologies using silicon oxide or silicon oxynitride as gate dielectric materials face issues such as increased leakage current and impurity diffusion, affecting the performance of MOS transistors, especially as device sizes shrink.
Innovation Solution
A method involving thermal annealing with an inert gas after removing the oxide layer to smooth the semiconductor substrate surface, followed by forming an insulating layer, a high-K gate dielectric layer, and a protective layer to reduce defects and leakage current, using materials like hafnium oxide and titanium nitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide or silicon oxynitride is used as gate dielectric material, then the fabrication process is simple, but leakage current increases and impurity diffusion occurs
Solution Approach 1:
The patent uses a composite gate dielectric structure consisting of silicon oxide layer and high-k dielectric layer (hafnium oxide, zirconium oxide, or tantalum oxide). The silicon oxide layer provides good interface quality and ease of fabrication, while the high-k dielectric layer provides high dielectric constant to reduce leakage current. This composite structure resolves the contradiction between fabrication simplicity and leakage current reduction.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing high-k materials (hafnium oxide with k≈25, zirconium oxide with k≈25, tantalum oxide with k≈27) to replace or supplement traditional silicon oxide. This parameter change enables lower leakage current while maintaining acceptable fabrication complexity through standard deposition techniques.
2Productivity
If device size is reduced for miniaturization, then integration density increases, but leakage current and impurity diffusion increase
Solution Approach 1:
The composite gate dielectric structure with high-k materials enables continued miniaturization by providing sufficient dielectric strength at reduced thicknesses. The high dielectric constant allows thinner effective oxide equivalent thickness while maintaining low leakage current, thus supporting higher integration density without sacrificing reliability.
3Ease of manufacture
If oxide layer is removed from semiconductor substrate, then surface is exposed for subsequent layer formation, but surface defects and carrier trapping centers increase
Solution Approach 1:
The patent performs preliminary thermal annealing treatment on the semiconductor substrate after oxide layer removal and before forming the gate dielectric layers. This preliminary action repairs surface defects and reduces carrier trapping centers, ensuring high-quality interfaces for subsequent layer formation while maintaining surface accessibility.
Solution Approach 2:
The patent uses inert gas (nitrogen or argon) atmosphere during the thermal annealing process to prevent oxidation and contamination of the exposed semiconductor substrate surface. This inert environment protects the surface while thermal annealing repairs defects, reducing carrier trapping centers without introducing new contaminants.
4Manufacturing precision
If thermal annealing is performed with reactive gas, then surface treatment is effective, but contamination and oxidation occur
Solution Approach 1:
The patent explicitly uses inert gas (nitrogen or argon) as the annealing atmosphere to eliminate oxidation and contamination during thermal treatment. This inert environment allows effective surface treatment through thermal annealing while preventing harmful reactions with the semiconductor substrate and previously formed layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces surface defects, carrier trapping centers, and leakage current, improving the reliability and performance of semiconductor devices by enhancing the smoothness and stability of the semiconductor substrate and dielectric layers.
Implementation Method 1
performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas
Implementation Method 2
performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas
Data Source
AI summary
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.