Semiconductor Substrate Lamination via Insulating Layer Mediator

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Solution Overview

Problem

The existing methods for manufacturing three-dimensional integrated circuits (LSIs) face challenges in achieving sufficient processing accuracy and avoiding damage to elements due to pressure application during substrate lamination, especially when the space between substrates is narrow, and the roughness of the insulating layer formed on the underside of the substrate affects electrical connections.

Innovation Solution

A semiconductor device manufacturing method involving the creation of through holes in substrates, deposition and patterning of insulating films, formation of conductive barrier films, and filling these holes with conductive material, with precise etching and polishing techniques to form Through Silicon Vias (TSVs), and using an insulating layer between substrates to align and connect them without pressure bonding, thus ensuring accurate microfabrication and reliable electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pressure bonding is applied to laminate substrates, then electrical connections between substrates are achieved, but damage to elements in the LSI occurs

Engineering Contradiction:
Improveelectrical connectionsVSAvoiddamage to elements
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an insulating layer as an intermediary between the substrates during the lamination process. This insulating layer is formed on the underside of the upper substrate before bonding, allowing the substrates to be laminated together without direct pressure contact between the substrate surfaces, thereby preventing damage to the LSI elements while still achieving electrical connections through the through electrodes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating layer is formed on the underside of the upper substrate before the lamination process. This preliminary action prepares the substrate surface in advance to prevent damage during bonding, eliminating the need for pressure bonding and protecting the elements from harm while enabling subsequent electrical connections

Inventive Principle:
Principle #10Preliminary action

2Volume of moving object

If the space between substrates is narrow, then substrate integration density is improved, but adhesive filling becomes difficult

Engineering Contradiction:
Improvesubstrate integration densityVSAvoidadhesive filling
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent removes the adhesive filling step entirely from the manufacturing process. By forming an insulating layer on the underside of the upper substrate before lamination, the substrates can be bonded together without requiring adhesive to fill the space between them, thus eliminating the difficulty of filling narrow spaces while maintaining high substrate integration density

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If insulating layer with large roughness is patterned, then manufacturing process is simplified, but processing accuracy deteriorates

Engineering Contradiction:
Improvemanufacturing processVSAvoidprocessing accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The insulating layer is formed on the underside of the upper substrate before lamination, serving as a pre-prepared surface that eliminates the need for subsequent patterning operations. This preliminary formation of the insulating layer with controlled properties avoids the accuracy issues associated with patterning rough surfaces while maintaining manufacturing efficiency

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the manufacturing process, enhances processing accuracy, and prevents damage to substrates during bonding, resulting in high-density, reliable semiconductor devices with improved electrical connections and reduced risk of substrate damage.

Implementation Method 1

filling these holes with conductive material

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

deposition and patterning of insulating films

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS8535977B2Semiconductor device manufacturing method
Publication Date: 2013.09.17 KIOXIA CORP
  • US8535977B2 patent drawing
  • US8535977B2 patent drawing
  • US8535977B2 patent drawing

AI summary

According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.