Semiconductor Substrate Metal Layer Reverse Stress Warpage
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Solution Overview
Problem
The coefficient of thermal expansion (CTE) mismatch between semiconductor chips and packaging substrates leads to thermal stresses and warpages, reducing product reliability and causing failure in reliability tests, especially when through silicon via interposers are thin.
Innovation Solution
A semiconductor substrate design featuring conductive through vias with exposed end surfaces, a metal layer sandwiched between two dielectric layers, and redistribution layers (RDL) on both surfaces to balance thermal stresses, with the metal layer providing reverse stress to mitigate warpage and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an interposer is made thin to meet miniaturization requirements, then the package size is reduced, but CTE mismatch between the interposer and packaging substrate causes thermal stresses and warpages
Solution Approach 1:
The patent changes the material composition of the interposer by incorporating a metal layer (such as copper) with a CTE value closer to that of the packaging substrate. This parameter change in material composition allows the interposer to maintain structural integrity and reduce warpage even when made thin, thereby resolving the contradiction between miniaturization and reliability
Solution Approach 2:
The patent employs a composite structure consisting of a silicon substrate with embedded through-silicon vias and a metal layer (e.g., copper) formed therein. This composite material design creates an interposer with tailored CTE properties that bridge the gap between the silicon chip and the organic packaging substrate, enabling thin interposer design without compromising reliability
2Manufacturing precision
If a through silicon via interposer is used to meet fine pitch requirements, then integration with semiconductor chips is improved, but CTE mismatch between the interposer and packaging substrate causes thermal stresses
Solution Approach 1:
The patent modifies the CTE parameter of the interposer by introducing a metal layer with intermediate CTE properties. This parameter change enables the interposer to maintain fine pitch integration capabilities while reducing the CTE mismatch with the packaging substrate, thereby minimizing thermal stresses during temperature cycling
Solution Approach 2:
The metal layer (such as copper) acts as an intermediary material between the silicon substrate and the organic packaging substrate. Its CTE value serves as a bridge, gradually transitioning from the low CTE of silicon to the high CTE of the organic substrate, thus reducing thermal stress concentration at the interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces CTE mismatch-induced warpage and enhances product reliability by balancing thermal stresses, ensuring stable performance even in thin substrates.
Implementation Method 1
the coefficient of thermal expansion (CTE) mismatch between a chip, which generally has a CTE of 3 ppm/° C., and a packaging substrate, which generally has a CTE of 18 ppm/° C., easily causes large thermal stresses and warpages to occur
Implementation Method 2
the metal layer formed between the first and second dielectric layers provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate
Data Source
AI summary
A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate.