Semiconductor Substrate Non-Coplanar Bonding Pads
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Solution Overview
Problem
Conventional semiconductor substrates with electroplating lines face challenges in size reduction due to increased trace pitch, which hinders the miniaturization of electronic products and increases manufacturing costs.
Innovation Solution
A semiconductor substrate design without electroplating lines, featuring an embedded conductive circuit layer with a surface treatment layer formed by electroplating on exposed portions, allowing for finer pitch and increased circuit layout flexibility, achieved through a manufacturing method involving a conductive layer, insulating layer, and selective etching to create non-coplanar surfaces for bonding pads and traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating lines are included in the circuit layout design to form surface treatment layer on bonding pads, then bonding reliability is improved, but trace pitch increases which is contrary to size reduction demand
Solution Approach 1:
The patent extracts the electroplating lines from the circuit layout by using a separate conductive layer (second conductive layer) that is electrically connected to the bonding pads through conductive vias. This allows the surface treatment layer to be formed on the bonding pads without including electroplating lines in the main circuit layout, thereby maintaining bonding reliability while reducing trace pitch and enabling finer circuit spacing.
Solution Approach 2:
The patent moves the electroplating function to a different dimensional plane by creating a separate second conductive layer that is stacked above the insulating layer containing the circuit traces. This vertical arrangement allows the surface treatment to be applied without interfering with the horizontal circuit layout, enabling finer pitch while maintaining bonding pad functionality.
2Ease of manufacture
If electroplating lines are used to connect bonding pads and conductive traces, then surface treatment layer formation is enabled, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the conductive structure into multiple independent layers: the first conductive layer contains the circuit traces, the second conductive layer provides electroplating connectivity, and conductive vias connect them. This segmentation allows the surface treatment function to be separated from the circuit layout design, simplifying the overall manufacturing process while enabling surface treatment layer formation on bonding pads.
Solution Approach 2:
The patent introduces conductive vias as intermediary elements that connect the first conductive layer (circuit traces) to the second conductive layer (electroplating layer). These vias act as mediators that enable surface treatment layer formation without requiring electroplating lines to be integrated into the main circuit layout, thereby reducing circuit layout complexity while maintaining manufacturing capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced trace pitch, enhanced circuit density, and lower manufacturing costs by eliminating the need for electroplating lines, thereby supporting the miniaturization of electronic components.
Implementation Method 1
forming a surface treatment layer on the first portion by electroplating
Data Source
AI summary
A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.