Semiconductor Substrate with Patterned Conductive Layers for Heat Dissipation
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Solution Overview
Problem
Existing semiconductor packages face inefficiencies in heat dissipation, leading to potential electrical circuit failure due to excessive heat buildup, as conventional methods often rely on heat sinks that primarily dissipate heat in one direction with inadequate dissipation in other directions.
Innovation Solution
The implementation of a semiconductor package design that includes a dielectric structure with patterned conductive layers on scribe lines, allowing for increased copper density and effective heat dissipation through these layers, which are wider than traditional conductive wiring trenches, thereby creating a more efficient heat-conducting channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a heat sink is placed in thermal contact with one surface of the semiconductor device, then heat dissipation in one direction is improved, but heat dissipation in other directions remains inadequate
Solution Approach 1:
The patent transitions from one-dimensional heat dissipation (single heat sink on one surface) to three-dimensional heat dissipation by incorporating conductive layers throughout the substrate thickness and adding side surface heat sinks, creating heat dissipation pathways in multiple spatial dimensions
Solution Approach 2:
The heat dissipation system is segmented into multiple independent heat sinks positioned at different locations and orientations (top surface heat sink, side surface heat sinks), each handling heat in specific directions, collectively providing comprehensive thermal management
2Temperature
If conventional heat sink approaches are used, then some heat dissipation is achieved, but size and power limitations occur
Solution Approach 1:
The patent merges the substrate structure with heat dissipation functionality by integrating conductive layers directly into the substrate and combining multiple heat sinks (top and side surfaces) into a unified thermal management system, eliminating the need for separate, bulky heat dissipation components
Solution Approach 2:
By utilizing the side surfaces and internal substrate volume for heat dissipation in addition to the top surface, the patent reduces the footprint and overall size of the package while maintaining effective heat dissipation capability
3Temperature
If copper density is increased in scribe line regions, then heat dissipation is improved, but substrate warpage may occur
Solution Approach 1:
The patent applies local quality by concentrating high copper density specifically in the scribe line regions rather than uniformly throughout the substrate, creating localized heat dissipation channels where thermal management is most needed while maintaining substrate structural integrity
Solution Approach 2:
The patent changes the copper density parameter locally in scribe line regions, increasing it from conventional levels to enhanced levels, thereby improving thermal conductivity and heat dissipation capability in these specific areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation without increasing the package size or manufacturing costs, while also alleviating substrate warpage issues by utilizing the scribe line regions with higher copper density for improved thermal management.
Implementation Method 1
Some embodiments of the present disclosure provide a semiconductor package, including a dielectric structure having a bottom surface configured to be proximal to a solder bump and a side surface connecting to the bottom surface, a first patterned conductive layer proximal to a top surface of the dielectric structure, the top surface being opposite to the bottom surface, a second patterned conductive layer extending on the side surface
Data Source
AI summary
The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.