Semiconductor Device Substrate Resistance Reduction
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Solution Overview
Problem
Conventional trench devices exhibit high forward on-resistance due to substrate resistance, which complicates the production process and reduces forward conduction capability, while existing substrate thinning methods lead to unevenness and stress imbalance.
Innovation Solution
A semiconductor device with an N+ substrate featuring openings and epitaxial layers, including P++ area rings and groove structures, and a terminal area with N+ field stop and P+ guard rings, along with a Schottky contact and passivation layer, is designed to reduce substrate resistance and simplify the production process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate thinning technology is used to optimize substrate resistance, then forward conduction capability is improved, but substrate unevenness and stress imbalance occur, making fine processes difficult
Solution Approach 1:
The patent introduces a porous layer in the drift region of the semiconductor device. This porous structure reduces the effective resistance of the substrate without requiring thinning, thereby improving forward conduction capability while maintaining substrate integrity and avoiding unevenness and stress imbalance issues.
2Reliability
If substrate thinning is performed to reduce substrate resistance, then production process complexity increases
Solution Approach 1:
The porous layer is formed through a straightforward epitaxial growth process rather than complex thinning operations. This approach reduces substrate resistance while avoiding the complex steps of thinning, polishing, and stress management required by conventional substrate thinning methods.
Data Source
AI summary
The present disclosure discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: an N+ substrate, a plurality of openings opening toward a back surface formed in the N+ substrate; an N− epitaxial layer formed on the N+ substrate, the N− epitaxial layer including: an active area epitaxial layer including a plurality of P++ area rings and a plurality of groove structures, wherein single groove structure is formed on single P++ area ring; a terminal area epitaxial layer including an N+ field stop ring and a plurality of P+ guard rings; a Schottky contact formed on the active area epitaxial layer, a passivation layer formed on the terminal area epitaxial layer, and ohmic contacts formed on the back surface of the N+ substrate and in the plurality of openings.