Semiconductor Substrate Structure to Neutralize RF Parasitic Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of III-V materials on silicon substrates for RF applications faces challenges due to the formation of parasitic surface conductive layers, which cause RF losses and harmonic generation, as the resistivity of the silicon layer decreases during high-temperature epitaxial growth, and existing solutions like trap-rich layers are either complex or ineffective in mitigating these issues.
Innovation Solution
A substrate structure is proposed with a base substrate, a dielectric layer, a trap-rich layer, and a crystalline semiconductor layer, where the trap-rich layer is positioned between the dielectric and crystalline semiconductor layers to neutralize parasitic surface conductive layers, reducing RF energy losses by trapping free charges and compensating for positive charges in the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If III-V materials are grown on high resistivity silicon substrate for RF applications, then low cost and high volume production are achieved, but parasitic surface conductive layers form causing RF losses and harmonic generation
Solution Approach 1:
The patent applies preliminary action by forming a trap-rich layer in the silicon substrate before epitaxial growth of III-V materials. This trap-rich layer is created through ion implantation or other doping methods prior to growing the compound semiconductor layers, so that traps are already in place to capture diffusing III-V atoms and prevent parasitic conductive layer formation during subsequent RF device operation
Solution Approach 2:
The trap-rich layer acts as an intermediary between the high resistivity silicon substrate and the III-V material stack. It mediates the interaction by providing a zone with high trap density that captures diffusing III-V atoms, preventing them from reaching the interface and forming parasitic conductive layers, thus protecting the RF performance while maintaining the benefits of silicon substrate integration
2Reliability
If trap-rich layer is formed underneath oxide layer of SOI wafer, then free charges in base substrate are neutralized, but this solution is not effective for mitigating losses caused by III-V layers grown on Si top layer
Solution Approach 1:
The patent applies local quality by positioning the trap-rich layer at a specific location within the silicon substrate - specifically in the lower portion of the high resistivity silicon layer, close to the interface where III-V materials will be grown. This localized placement ensures that traps are concentrated exactly where III-V atoms diffuse during epitaxial growth, maximizing the neutralization effect precisely at the critical interface region rather than distributing traps uniformly throughout the substrate
3Manufacturing precision
If laser irradiation is used to form trap-rich layer after epitaxial growth, then trap-rich layer is formed at interface, but the method is complex and impact on substrate characteristics is unpredictable
Solution Approach 1:
The patent applies preliminary action by forming the trap-rich layer through ion implantation or doping methods before the epitaxial growth of III-V materials, rather than using post-growth laser irradiation. This approach simplifies the overall process by integrating trap-rich layer formation into the substrate preparation stage, avoiding the need for complex laser processing equipment and unpredictable post-growth modifications while ensuring traps are in place before III-V atoms begin diffusing
Solution Approach 2:
The patent replaces the mechanical/optical laser irradiation method with a more controlled ion implantation or thermal diffusion process. Instead of using high-energy laser beams that can cause unpredictable structural modifications, the invention uses well-established semiconductor processing techniques (ion implantation or thermal diffusion) to create the trap-rich layer, providing better process control, reproducibility, and integration with existing CMOS fabrication lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a low-loss substrate suitable for growing III-V materials, effectively reducing RF energy losses and enabling the production of high-performance semiconductor devices with improved switch linearity and reduced harmonic generation.
Implementation Method 1
the trap-rich layer is positioned between the dielectric and crystalline semiconductor layers to neutralize parasitic surface conductive layers, reducing RF energy losses by trapping free charges and compensating for positive charges in the dielectric layer
Data Source
AI summary
In one aspect, a substrate includes a base substrate, a dielectric layer directly on the base substrate, a trap-rich layer directly on the dielectric layer, and a crystalline semiconductor layer directly on the trap-rich layer. The dielectric layer may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate can be suitable to epitaxially grow on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor. One application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable to process in and/or on the layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, can enable the neutralization of a parasitic surface conductive (PSC) layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer. The disclosed technology is equally related to methods of producing the substrate of the disclosed technology.