3D Stacked Semiconductor Device with Substrate Segmentation
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the size of unit cells and line widths due to lithography resolution limitations and material constraints, hindering further integration density and cost-effectiveness.
Innovation Solution
A semiconductor device design featuring a memory array on one substrate and a peripheral circuit on another, with electrical connection via conductive plugs through via holes, allowing for different substrate sizes, shapes, and materials, and enabling flexible placement and connection configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lithography resolution and material limitations are overcome to reduce unit cell size and line width, then integration density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the semiconductor device into multiple substrates (first substrate for memory array, second substrate for peripheral circuit), allowing each to be manufactured independently at optimal process nodes and then combined through wafer bonding, thereby achieving high integration density without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by bonding multiple substrates together vertically, enabling integration density to increase in the vertical dimension rather than requiring further reduction of lateral dimensions which would hit lithography limits
2Quantity of substance
If unit cell size and line width are reduced below threshold values, then integration density increases, but manufacturing becomes infeasible due to lithography resolution limitations
Solution Approach 1:
The patent segments the device into multiple substrates that can each be manufactured at feasible process nodes using existing lithography technology, avoiding the need to push single-substrate dimensions below lithography resolution limits while still achieving high overall integration density through vertical stacking
Solution Approach 2:
The patent performs preliminary manufacturing of memory arrays and peripheral circuits on separate substrates at optimal process nodes before final assembly, allowing each component to be manufactured under ideal conditions rather than forcing all components onto a single substrate with overly aggressive scaling requirements
3Device complexity
If all components are integrated on a single substrate, then device complexity is reduced, but substrate size and manufacturing cost increase
Solution Approach 1:
The patent divides the device into multiple smaller substrates (first substrate for memory array, second substrate for peripheral circuit), reducing the area of each individual substrate while maintaining overall functional integration through wafer bonding, thereby lowering manufacturing costs associated with large substrate processing
Solution Approach 2:
The patent moves from two-dimensional planar layout to three-dimensional vertical stacking, allowing high integration to be achieved in the vertical dimension rather than requiring a single large substrate in the lateral dimension, thus reducing substrate area and associated manufacturing costs
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other.