Semiconductor Substrate With Stacked Metal Oxide Transistors
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Solution Overview
Problem
Metal oxide semiconductor thin-film transistors face limitations in carrier mobility, making it difficult to achieve high current output and design pixel layouts for high-resolution displays, as they require increased layout area.
Innovation Solution
A semiconductor substrate design featuring a first and second metal oxide semiconductor layer with specific transistor configurations, including non-overlapping and partially overlapping source and gate structures, and a second transistor with sub-transistors connected in parallel to enhance carrier mobility and reduce layout area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal oxide semiconductor thin-film transistor is used to provide high current output, then current output capability is improved, but layout area increases
Solution Approach 1:
The patent transitions from a planar single-layer transistor structure to a three-dimensional stacked structure with multiple metal oxide semiconductor layers arranged vertically. This dimensional change allows multiple transistors to share the same footprint area, effectively increasing current output capability without proportionally increasing layout area. The stacked configuration enables T1 and T2 to occupy overlapping horizontal spaces while maintaining electrical independence through vertical separation.
Solution Approach 2:
The patent merges multiple transistor functions into a compact stacked structure where T1 and T2 share common elements such as the gate electrode and insulating layers. The source and drain electrodes are configured to electrically connect both transistors, creating a combined structure that achieves high current output through parallel conduction paths while minimizing the overall layout area.
2Power
If carrier mobility of metal oxide semiconductor thin-film transistor is increased, then current output capability is improved, but layout area requirements increase
Solution Approach 1:
The patent employs multiple metal oxide semiconductor layers (first metal oxide semiconductor layer with T1, second metal oxide semiconductor layer with T2) stacked vertically to create parallel current conduction paths. This three-dimensional arrangement increases effective carrier mobility by providing multiple conduction channels within the same horizontal footprint, thereby improving current output capability without increasing layout area.
Solution Approach 2:
The patent uses composite structures combining multiple metal oxide semiconductor layers with different configurations. The first metal oxide semiconductor layer forms T1 with non-overlapping source and gate, while the second metal oxide semiconductor layer forms T2 with partially overlapping source and gate. This composite approach optimizes carrier transport properties and achieves high current output with compact area.
3Manufacturing precision
If first source and first gate are not overlapped, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies different structural configurations to different transistors within the same device. T1 uses a non-overlapping source-gate configuration for simplified manufacturing, while T2 uses a partially overlapping source-gate configuration for optimized electrical performance. This local differentiation allows each transistor to be optimized for its specific function while maintaining overall device integration.
Solution Approach 2:
The patent segments the transistor structure into distinct functional units (T1 and T2) with different source-gate overlap characteristics. T1 is segmented as a simple non-overlapping structure for easy fabrication, while T2 is segmented as a partially overlapping structure for enhanced performance. This segmentation allows independent optimization of each transistor type without compromising the other.
4Power
If second source and second gate are partially overlapped, then carrier mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements partial overlap between the second source and second gate in T2 to enhance carrier mobility in the channel region. The overlap is strategically positioned to maximize electrical performance while maintaining manufacturability. This local optimization of the gate-source interface improves carrier injection and transport without requiring excessive alignment precision across the entire device.
Data Source
AI summary
A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.