Semiconductor Substrate Stacking with Conductive Bumps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues such as poor structural configuration and delamination, which increases yield loss and manufacturing costs in chip-on-wafer-on-substrate (CoWoS) integration.
Innovation Solution
A semiconductor structure is developed with a first substrate, a first die bonded over it, and a second die bonded between the substrates using conductive bumps, minimizing electrical connections and improving electrical performance by embedding the second die within the substrate, thus reducing capacitance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips are assembled on a single semiconductor device in miniaturized scale, then greater functionality and integrated circuitry are achieved, but manufacturing complexity increases resulting in poor structural configuration and delamination
Solution Approach 1:
The patent divides the semiconductor device into multiple substrates (first substrate, second substrate, third substrate) that are stacked vertically. Each substrate can be manufactured and prepared separately, then assembled together through bonding interfaces. This segmentation allows each substrate to be optimized independently while achieving greater overall functionality through integration.
Solution Approach 2:
The patent transitions from a planar arrangement of chips to a three-dimensional stacked configuration. By utilizing the vertical dimension through multiple bonding interfaces between substrates, the device achieves higher integration density and functionality without increasing the footprint, thereby managing manufacturing complexity more effectively.
2Productivity
If manufacturing operations are implemented within a small semiconductor device, then integrated circuitry is increased, but structural configuration deteriorates and delamination occurs
Solution Approach 1:
The patent segments the device into multiple substrates with distinct bonding interfaces, allowing each substrate to be manufactured with optimized structural configuration for its specific function. This reduces the risk of delamination by ensuring each bonding interface is designed and manufactured under controlled conditions rather than attempting to fit all operations into a single small device.
Solution Approach 2:
The patent employs a nested structure where multiple substrates are stacked and bonded together, with each substrate containing functional elements. This nested arrangement allows integrated circuitry to be distributed across multiple layers, maintaining structural integrity at each level while achieving high overall integration.
3Adaptability or versatility
If conventional CoWoS manufacturing is used, then chip integration is achieved, but yield loss increases due to manufacturing deficiencies
Solution Approach 1:
By dividing the device into multiple substrates that can be manufactured and tested separately before final assembly, the patent enables intermediate quality checks and defect identification at each bonding interface. This segmentation approach allows for better yield management by isolating manufacturing issues to specific substrates rather than affecting the entire device.
Solution Approach 2:
The patent performs preliminary manufacturing and bonding operations on individual substrates before final assembly. This preliminary action allows for quality control and defect detection at intermediate stages, enabling corrective measures to be taken before complete device assembly, thereby reducing overall yield loss.
Data Source
AI summary
A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.