Semiconductor Device Substrate Step for CMP Planarization
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Solution Overview
Problem
In semiconductor manufacturing, the progression to nanometer technology nodes has made it challenging to control the flatness of underlying layers during lithography operations, particularly due to height differences between non-volatile memory cells and peripheral devices, affecting chemical mechanical polishing (CMP) processes.
Innovation Solution
A method is introduced where a substrate is etched to create a 'step' between the non-volatile memory cell and peripheral device areas, followed by the formation of specific layers and their subsequent removal to ensure a controlled height difference, facilitating easier CMP operations and reducing the area where device placement should be avoided.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing is used to planarize the underlying layer, then flatness is improved, but the process becomes more complex and time-consuming due to height differences between memory cell and peripheral device areas
Solution Approach 1:
The substrate surface is segmented into two distinct levels: a first level for memory cell formation and a second level for peripheral device formation. This segmentation is achieved by selectively etching the substrate to create a step structure, where the etched region corresponds to the memory cell area. By dividing the substrate into separate height zones, the patent eliminates the need for complex CMP processes to handle height differences, as each region can be processed independently at its appropriate level.
Solution Approach 2:
The substrate etching step is performed in advance, before forming the memory cell and peripheral device structures. This preliminary action creates the height difference and defines the boundary region upfront, allowing subsequent layer formation and processing to proceed without requiring additional planarization steps. The step structure is established before any device-specific layers are deposited, enabling simpler and more efficient downstream processing.
2Productivity
If the boundary region area is reduced, then manufacturing efficiency is improved, but the transition surface size is minimized which could affect device placement flexibility
Solution Approach 1:
The patent applies different structural characteristics to different regions of the substrate. The boundary region is specifically designed with a controlled width (5 nm to 500 nm) and is positioned at a predetermined distance from the substrate edge. This localized structural definition optimizes the transition zone for manufacturing efficiency while maintaining sufficient space for device placement. The specific dimensions and positioning of the boundary region are tailored to balance manufacturing efficiency with device placement requirements, ensuring that critical dimensions are controlled where needed without unnecessarily constraining overall design flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area of the boundary region between memory cell and peripheral areas, enhancing CMP planarization and reducing the size of the transition surface, thereby improving manufacturing efficiency and device performance.
Implementation Method 1
a substrate is etched to create a 'step' between the non-volatile memory cell and peripheral device areas
Implementation Method 2
chemical mechanical polishing operations have played an important role for planarizing the underlying layer
Data Source
AI summary
In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.