Semiconductor Substrate Through Openings Reduce Parasitic Inductance
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Solution Overview
Problem
Existing integrated semiconductor devices face limitations in signal and power supply performance due to the length and parasitic resistance/inductance of connections in BGA packages, particularly when contact pads are densely arranged, leading to voltage drops and frequency issues.
Innovation Solution
The integrated semiconductor device features a supporting substrate with through openings and steps, allowing flexible arrangement of contact pads and bonding wires, enabling shorter connections and reduced parasitic effects, while combining the robustness and cost-effectiveness of wire bonding with the density and flexibility of flip chip techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wire bonding technique is used with contact pads arranged in multiple lines, then the number of contacts can be increased, but the connection length increases leading to higher parasitic resistance and inductance
Solution Approach 1:
The patent introduces a third dimension by creating recesses in the substrate that allow bonding wires to pass through vertically rather than traveling only on the surface. This dimensional change reduces the effective path length of connections while maintaining the ability to accommodate multiple contact pads, thereby reducing parasitic resistance and inductance without limiting the number of contacts.
Solution Approach 2:
The recesses act as intermediary structures that facilitate shorter wire paths. By providing these intermediate recessed regions, the substrate enables bonding wires to achieve directer routes between contact pads, reducing connection length and associated parasitic effects while still supporting high contact density.
2Quantity of substance
If contact pads are arranged in multiple lines to increase contact capacity, then more connections can be made, but connection length increases causing voltage drops
Solution Approach 1:
The recesses create a vertical dimension for wire routing, allowing power and signal connections to reach contact pads with shorter effective lengths. This reduces the resistive losses and voltage drops that would otherwise occur with longer surface-level wire paths, while maintaining the ability to accommodate multiple contact pads in different locations.
3Length of moving object
If flip chip technique is used, then connection length is minimized, but manufacturing cost increases and reliability decreases
Solution Approach 1:
The recesses serve as intermediary structures that enable wire bonding to achieve connection lengths comparable to flip chip technology. By providing these recessed pathways, the substrate allows bonding wires to take more direct routes, minimizing connection length without requiring the complex flip chip assembly process, thereby maintaining manufacturing simplicity and reliability.
Data Source
AI summary
An integrated semiconductor device and a method for manufacturing the integrated semiconductor device are disclosed. In an embodiment an integrated semiconductor device includes a supporting substrate having a first substrate face and a second substrate face opposite to the first substrate face, a semiconductor die having a first die face coupled to the first substrate face of the supporting substrate, the first die face including first die contact pads, wherein the supporting substrate has at least one through opening, wherein the first die contact pads are arranged facing the through opening, and wherein the supporting substrate comprises first substrate contact pads connected by first bonding wires to the respective first die contact pads through the through opening.