Semiconductor Substrate Miniaturization via Wafer Pattern Transfer
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Solution Overview
Problem
Conventional semiconductor devices have thick substrates and conductive patterns, leading to increased costs and reduced integration levels due to larger line widths in packaging processes compared to fabrication processes.
Innovation Solution
A semiconductor device and manufacturing method that utilize a pattern layer on a wafer with reduced thickness and fine conductive patterns, allowing for miniaturization and improved integration by forming a substrate with a thickness range of 1 to 10 μm and line widths of 0.1 to 20 μm, and including encapsulants and conductive members for enhanced connectivity and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional substrate and conductive pattern dimensions are used in semiconductor packaging, then structural strength and electrical connectivity are ensured, but device size increases and integration level decreases
Solution Approach 1:
The patent changes the dimensional parameters of the substrate and conductive patterns by transferring them from the packaging process to the FAB process. The substrate thickness is reduced to 1-10 μm and conductive pattern line widths are reduced to 0.1-20 μm, achieving miniaturization while maintaining electrical functionality through parameter optimization in the fabrication stage.
Solution Approach 2:
The conductive patterns and substrate structures are formed in advance during the FAB process before the packaging stage. This preliminary formation of fine conductive patterns and thin substrates allows subsequent packaging processes to work with pre-miniaturized structures, achieving both small device size and high integration without compromising structural integrity.
2Ease of manufacture
If conventional substrate thickness and conductive pattern dimensions are used, then structural integrity is maintained, but manufacturing cost increases
Solution Approach 1:
The patent reduces substrate thickness from conventional 200-300 μm to 1-10 μm and optimizes conductive pattern dimensions, which directly reduces material consumption and manufacturing cost. The parameter changes enable thinner substrates and finer patterns to be manufactured with acceptable yield, lowering overall production expenses.
Solution Approach 2:
The patent copies the conductive pattern formation process from conventional packaging to the FAB process, where finer and more precise patterning is already established. This copying of the fabrication approach to packaging enables cost-effective production of miniaturized structures using existing FAB capabilities.
3Manufacturing precision
If fine conductive patterns with small line widths are formed, then integration level improves, but manufacturing difficulty increases due to process limitations
Solution Approach 1:
The conductive patterns are formed in advance during the FAB process when fine patterning capabilities are already available. This preliminary formation of precise conductive patterns before packaging avoids the need to develop complex new packaging processes for fine patterning, reducing overall process complexity while achieving high manufacturing precision.
Solution Approach 2:
The patent uses the FAB process as an intermediary to create the fine conductive patterns that would otherwise require complex packaging processes. By having the FAB process produce the miniaturized conductive structures, the patent avoids direct complexity in the packaging stage while achieving high precision patterns.
Data Source
AI summary
Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a substrate using a pattern layer implemented on a wafer in a semiconductor fabrication (FAB) process. In one exemplified embodiment, the manufacturing method of the semiconductor device includes preparing a first semiconductor die including a plurality of through electrodes and a plurality of first conductive pillars, mounting the first semiconductor die to connect the first conductive pillars to the pattern layer provided on a wafer, forming a first encapsulant to cover the pattern layer and the first semiconductor die, mounting a second semiconductor die to electrically connect second conductive pillars provided in the second semiconductor die to the plurality of through electrodes exposed to a second surface of the first semiconductor die, and removing the wafer from a first surface of the pattern layer.