Semiconductor Substrate Assembly for CTE Warpage Compensation
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Solution Overview
Problem
Semiconductor substrates with multi-layer circuit structures face warpage issues due to coefficient of thermal expansion (CTE) mismatch, leading to reduced yields and electrical performance, especially as the number of layers increases.
Innovation Solution
The semiconductor substrate is manufactured by forming separate circuit structures with different CTE characteristics and then assembling them, allowing for electrical connection and offsetting warpage stresses, thereby reducing warpage and improving yields and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-layer circuit structure is formed sequentially in the substrate, then the circuit functionality is improved, but warpage problems occur due to CTE mismatch and stress accumulation
Solution Approach 1:
The multi-layer circuit structure is divided into multiple separate circuit layers, each formed independently on different substrates. These segmented layers are then bonded together to form the complete multi-layer circuit, avoiding the stress accumulation that occurs during sequential formation on a single substrate.
Solution Approach 2:
Circuit layers with opposite warpage directions are bonded together to offset each other's stress. The patent specifically mentions bonding a first circuit layer with a first warpage direction to a second circuit layer with a second warpage direction opposite to the first, creating a counterbalancing effect that reduces overall substrate warpage.
2Reliability
If the number of layers in the multi-layer circuit structure is increased, then the circuit performance is improved, but warpage problems become more obvious
Solution Approach 1:
Instead of forming all layers sequentially on one substrate, the circuit is segmented into multiple independent layers that can be manufactured separately and then assembled. This segmentation allows each layer to be optimized independently while reducing cumulative warpage effects.
Solution Approach 2:
The patent employs composite substrate structures with different material properties to achieve CTE matching. By using composite materials with appropriate thermal expansion coefficients, the overall warpage is reduced even as the number of circuit layers increases.
3Shape
If separate circuit structures with different CTE characteristics are assembled, then warpage stress is offset, but the manufacturing process complexity increases
Solution Approach 1:
Circuit layers are pre-formed on separate substrates with predetermined warpage characteristics before final assembly. This preliminary action allows for precise control of each layer's properties and simplifies the final bonding process, as the layers are already prepared with the correct specifications.
Solution Approach 2:
The patent utilizes changes in material parameters, particularly CTE values, to achieve warpage compensation. By selecting materials with specific thermal expansion coefficients for different layers, the overall structure achieves stress balance without requiring complex manufacturing processes.
Data Source
AI summary
A semiconductor substrate includes a first circuit structure and a second circuit structure. The first circuit structure includes a first circuit layer. The first circuit layer includes a first dielectric layer. The second circuit structure includes a second circuit layer. The second circuit layer includes a second dielectric layer. The second circuit structure is disposed on the first circuit structure and is electrically connected to the first circuit structure to constitute the semiconductor substrate. A manufacturing method of the semiconductor substrate is also provided.