Semiconductor Super-Junction Impurity Control via Mass Measurement

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Solution Overview

Problem

Semiconductor devices with super-junction structures face challenges in maintaining a small difference in impurity amounts between conductivity type semiconductor regions, affecting breakdown voltage and on-resistance, which existing manufacturing methods struggle to accurately control.

Innovation Solution

A method for manufacturing semiconductor members involves measuring the mass of semiconductor substrates before and after forming openings, adjusting the impurity concentration of the second conductivity type semiconductor layer based on the mass difference to achieve a reduced impurity difference between n-type and p-type pillar regions, thereby controlling the p-type impurity concentration in the p−-type semiconductor layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing methods are used to form super-junction structures, then the manufacturing process is simple, but the impurity amount difference between first conductivity type and second conductivity type semiconductor regions cannot be controlled accurately

Engineering Contradiction:
Improveimpurity amount controlVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent measures the mass of the semiconductor substrate before forming openings and after forming openings to determine the actual cross-sectional area of the second conductivity type semiconductor layer. This preliminary measurement action allows subsequent adjustment of impurity concentration to achieve accurate impurity amount control between different conductivity type regions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses mass measurement data as feedback to adjust the impurity concentration in the second conductivity type semiconductor layer. By comparing the mass difference before and after opening formation, the system determines the actual area and adjusts impurity concentration accordingly, creating a closed-loop control system for precise impurity amount control.

Inventive Principle:
Principle #23Feedback

2Reliability

If the impurity concentration is not adjusted based on mass difference, then the manufacturing process is fast, but the breakdown voltage and on-resistance performance deteriorate

Engineering Contradiction:
Improvebreakdown voltage and on-resistanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces direct measurement of the semiconductor layer cross-sectional area with mass measurement of the substrate. By measuring mass before and after opening formation and calculating the difference, the system indirectly determines the actual area of the second conductivity type layer, enabling precise impurity concentration adjustment without complex direct measurement equipment.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Manufacturing precision

If fixed impurity concentration is used in second conductivity type semiconductor layer, then the manufacturing process is simple, but the impurity amount difference between regions cannot be minimized

Engineering Contradiction:
Improveimpurity amount uniformityVSAvoidprocess simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the impurity concentration parameter in the second conductivity type semiconductor layer based on measured mass differences. Instead of using a fixed impurity concentration, the system adjusts the concentration to match the actual cross-sectional area, ensuring that the impurity amount (concentration × area) is equalized between first and second conductivity type regions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11658077B2Method for manufacturing semiconductor member and method for manufacturing semiconductor device
Publication Date: 2023.05.23 KK TOSHIBA
  • US11658077B2 patent drawing
  • US11658077B2 patent drawing
  • US11658077B2 patent drawing

AI summary

According to one embodiment, a method for manufacturing a semiconductor member is disclosed. The method can include measuring a first mass of a semiconductor substrate including a first semiconductor layer of a first conductivity type. The method can include forming a first opening in an upper surface of the first semiconductor layer. The method can include measuring a second mass of the semiconductor substrate in which the first opening is formed. In addition, the method can include when forming a second semiconductor layer of a second conductivity type in the first opening, changing an impurity concentration of the second conductivity type in the second semiconductor layer according to a difference in mass between the first mass and the second mass.