Semiconductor Device Super Junction Termination Region Optimization
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Solution Overview
Problem
Semiconductor devices with super junction structures face challenges in maintaining breakdown voltage in the termination region, leading to potential malfunction due to high electric potential and increased hole current, especially when manufactured using silicon carbide or silicon semiconductors, where hole mobility is lower than electron mobility.
Innovation Solution
The semiconductor device incorporates a design with alternating p-type and n-type pillar layers in both the active and termination regions, with a larger pillar pitch in the termination region compared to the active region, ensuring that the product of pillar width and impurity concentration remains consistent across both regions, thereby reducing hole current and improving breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity concentration in the termination region is reduced to improve breakdown voltage, then breakdown voltage is improved, but hole current increases and electric potential rises causing malfunction
Solution Approach 1:
The patent applies different impurity concentration levels to different regions: the active region maintains higher impurity concentration for low on-resistance, while the termination region uses lower impurity concentration for high breakdown voltage. This local differentiation resolves the contradiction by optimizing each region for its specific function rather than using a uniform concentration throughout the drift layer.
Solution Approach 2:
The drift layer is segmented into distinct active region and termination region with different impurity concentrations. The termination region is further divided into first and second termination regions with progressively lower impurity concentrations, creating a gradient structure that manages hole current while maintaining breakdown voltage.
2Object-generated harmful factors
If pillar pitch in the termination region is increased to reduce hole current, then hole current is reduced, but device area increases
Solution Approach 1:
The pillar pitch is optimized locally for each region: smaller pitch in the active region for high current handling, and larger pitch in the termination region for reduced hole current. This local differentiation achieves hole current reduction without unnecessarily increasing the overall device area.
Solution Approach 2:
The termination region uses a larger pillar pitch than the active region, applying excessive spacing specifically where needed to reduce hole current, while the active region maintains optimal spacing for current conduction. This partial application of larger pitch minimizes the overall area impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively lowers electric potential in the termination region and enhances breakdown voltage, reducing the risk of malfunction by minimizing hole current and improving resistance characteristics.
Implementation Method 1
when the drift layer has a conductivity type of an n type, a depletion layer extends from a pn junction surface between the p-type pillar layer and the n-type pillar layer
Implementation Method 2
a current flows through the drift layer provided on the semiconductor substrate
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate. First and second pillar layers, of respective first and second conductivity types, are alternately provided in a direction in parallel with a main surface in an active region of the semiconductor layer and in a termination region. A pillar pitch in the termination region is set to be larger than a pillar pitch in the active region. A product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers.