Semiconductor Super-Junction Device Vertical Doped Regions
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Solution Overview
Problem
As semiconductor devices shrink in size, they face challenges in maintaining driving currents and reducing on-resistance while sustaining high breakdown voltages, due to reduced surface area for doped regions which affects their performance.
Innovation Solution
The development of a semiconductor device with a super-junction structure that includes a semiconductor layer with alternating doped regions and a gate structure, where the doped regions are formed using ion implantation and diffusion processes to increase the cross-sectional area without increasing the surface area, and deep trench isolation is used to prevent latch-up effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device size is reduced, then the integration density increases, but the driving current decreases and on-resistance increases due to reduced surface area of doped regions
Solution Approach 1:
The patent transitions from a planar super-junction structure to a three-dimensional vertical structure by forming doped regions that extend deeper into the semiconductor layer. The doped regions are created with increased depth through controlled implantation and diffusion processes, effectively utilizing the vertical dimension to maintain sufficient doped region volume and surface area for adequate driving current even as the lateral device footprint is reduced.
2Volume of moving object
If the device size is reduced, then the integration density increases, but the on-resistance increases due to reduced cross-sectional area of doped regions
Solution Approach 1:
The patent addresses the on-resistance issue by extending doped regions vertically deeper into the semiconductor layer. This vertical extension increases the cross-sectional area available for current flow through the doped regions, thereby reducing on-resistance despite the reduced lateral device dimensions. The depth of doped regions is precisely controlled through implantation energy and diffusion time parameters.
3Reliability
If alternating doped regions are formed to maintain high breakdown voltage, then the breakdown voltage is sustained, but the manufacturing complexity increases due to multiple ion implantation and diffusion steps
Solution Approach 1:
The patent maintains the alternating doped region structure characteristic of super-junction devices, which is essential for achieving high breakdown voltage. The structure segments the semiconductor layer into alternating regions of first and second conductivity types, creating a balanced charge distribution that enables high voltage blocking capability. While the structure is complex, the manufacturing process uses standard segmented implantation and diffusion steps that are industrially feasible.
Solution Approach 2:
The patent optimizes the alternating doped region structure by precisely controlling implantation doses, energies, and diffusion temperatures to achieve the desired dopant profiles. By adjusting these parameters, the patent maintains the required alternating pattern for high breakdown voltage while potentially simplifying the overall process through optimized process windows and reduced cycle times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances driving currents and reduces on-resistance while maintaining high breakdown voltages, even as the device size decreases, by increasing the thickness and cross-sectional area of doped regions within the semiconductor layer.
Implementation Method 1
forming a first doped region in a portion of the semiconductor layer adjacent to a side of the opening
Implementation Method 2
forming a first doped region in a portion of the semiconductor layer adjacent to a side of the opening
Data Source
AI summary
A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type.