Semiconductor Super Junction Void Control via Eaves Mask
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with a super junction structure face challenges in achieving a flat polished surface due to voids in the p-type pillar layers, which affects the yield and performance of the devices by introducing unevenness and potential defects.
Innovation Solution
A method involving the formation of a mask with an eaves-like projection during epitaxial growth, where the opening width is controlled to ensure the void is confined below the polished surface, utilizing the difference in growth rates of silicon surfaces ({110} and {111} surfaces) to prevent void exposure and achieve a flat surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If p-type pillar layers are formed by epitaxial growth in trenches, then the super junction structure can be created to achieve low on-resistance beyond material limit, but voids remain in the p-type pillar layers causing non-flat polished surfaces
Solution Approach 1:
The mask member is formed with an eaves-like projection that protrudes into the trench before epitaxial growth occurs. This preliminary structural feature guides the epitaxial growth process to form the p-type pillar layer with a specific shape that prevents void formation, ensuring flat polished surface from the beginning of the growth process
Solution Approach 2:
The invention changes the geometric parameters of the mask member by forming an eaves-like projection with specific dimensions (protruding distance d1, width d2) relative to the trench dimensions (width W1, depth W2). These parameter changes control the epitaxial growth morphology to eliminate voids while maintaining the required pillar structure
2Manufacturing precision
If the opening width in the mask member is reduced to confine voids below the polished surface, then the void position becomes controllable, but the manufacturing process complexity increases
Solution Approach 1:
The mask member has non-uniform local structure with an eaves-like projection that creates different opening widths at different locations. The projection width d2 is specifically designed to be smaller than the trench width W1, creating a localized narrow opening region that confines voids below the polished surface while maintaining overall structural simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a flat surface during polishing, increasing the yield of semiconductor devices by controlling the void position and preventing defects, thereby improving the manufacturing process efficiency.
Implementation Method 1
forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth
Data Source
AI summary
A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member; etching the first-conductivity-type semiconductor region exposed to the opening to form a trench having a larger diameter than the opening and an eaves-like mask projected above the trench and made of the mask member; and forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth to form a structure section in which the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region are alternately repeated in a direction generally parallel to a major surface of the semiconductor layer.