Semiconductor Package Support Post Layout for Void-Free Bonding
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Solution Overview
Problem
The existing semiconductor packages face issues with voids in the underfill layer, bonding failures, and stress in semiconductor chips due to warpage and interference between connection terminals, leading to reduced productivity and yield.
Innovation Solution
A semiconductor package design that includes a redistribution structure, a semiconductor chip, conductive filler, and support posts, where the support posts are spaced apart from the conductive filler and insulated by a passivation layer, ensuring consistent gaps and reduced stress through the use of solder bumps and conductive fillers to improve bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gap between connection terminals is increased to prevent interference, then connection reliability is improved, but the area occupied by the semiconductor package increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, placing connection terminals at different vertical levels through multiple layers. This allows terminals to be positioned closer horizontally while maintaining sufficient vertical separation to prevent interference, thus reducing package area while preserving connection reliability.
Solution Approach 2:
The connection terminals are divided into multiple groups located on different layers, with each layer containing a subset of terminals. This segmentation allows for optimized spacing within each layer while utilizing vertical space to accommodate the total number of terminals, reducing the overall package footprint.
2Device complexity
If support posts are placed close to conductive filler to maximize space utilization, then manufacturing complexity is reduced, but bonding failure risk increases
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions: support posts are positioned at specific locations away from conductive filler to provide mechanical support, while conductive filler is placed in designated areas for electrical connection. This localized differentiation ensures both structural integrity and electrical functionality without compromising bonding reliability.
3Reliability
If underfill layer is applied to fill all gaps to prevent voids, then connection reliability is improved, but manufacturing time increases
Solution Approach 1:
The patent incorporates support posts and conductive filler in predetermined positions before applying the underfill layer. This preliminary arrangement ensures that the underfill can be applied more efficiently without requiring excessive time to navigate complex geometries, while still achieving complete gap filling and preventing voids for improved connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces voids in the underfill layer, prevents bonding failures, and minimizes stress in the semiconductor chip, thereby enhancing the productivity and yield of the semiconductor package by ensuring consistent connections and reduced thermal expansion-related issues.
Implementation Method 1
a solder bump at one end of the lower filler and connecting the semiconductor chip to the lower filler
Implementation Method 2
the second post may be insulated from the semiconductor chip by the passivation layer
Data Source
AI summary
A semiconductor package includes a redistribution structure, a semiconductor chip on the redistribution structure, a conductive filler between the redistribution structure and the semiconductor chip and connecting the redistribution structure to the semiconductor chip, and a support post between the redistribution structure and the semiconductor chip, the support post being spaced apart from the conductive filler, where the support post includes a first post on a top surface of the redistribution structure, and a second post including a first end connected to the first post and a second end oriented toward the semiconductor chip and supporting the semiconductor chip.