Semiconductor Device Surge Protection Circuit Topology
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Solution Overview
Problem
CMOS transistor circuits in semiconductor devices are vulnerable to surge currents, leading to potential breakdowns, especially when the protective circuit's withstand voltage characteristics are insufficient, and the even distribution of surge current is challenging, resulting in damage to transistors with non-standard gate width ratios.
Innovation Solution
A semiconductor device structure with a buffer circuit, an inverter circuit, and a dummy circuit, where the gate potential control circuit manages the gate potential of transistors based on the power wiring potential, ensuring equal operating speeds for pMOS and nMOS transistors and using dummy nMOS transistors to disperse surge currents effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surge current is concentrated at the protective circuit, then the CMOS transistor is protected, but the protective circuit experiences high stress and may fail
Solution Approach 1:
The protective circuit divides the surge current path into multiple segments with separate protective transistors. The first protective transistor handles surge currents with power supply potential at the gate, while the second protective transistor handles other surge conditions with control potential at the gate, distributing the current stress across multiple devices.
Solution Approach 2:
Multiple protective transistors are merged into a single protective circuit architecture that works together to handle different surge current scenarios. The parallel configuration of protective transistors with different gate connections combines their protection capabilities while distributing the stress burden.
2Adaptability or versatility
If the gate width ratio of pMOS and nMOS transistors is non-standard, then circuit design flexibility is improved, but surge current distribution becomes uneven and transistors may be damaged
Solution Approach 1:
The protective circuit uses transistors with specifically configured gate widths and gate connections tailored to local protection needs. The first protective transistor has its gate connected to power supply potential with a specific gate width, while the second protective transistor has its gate connected to control potential with a different gate width, creating localized protection characteristics that compensate for non-standard gate width ratios in the main circuit.
Data Source
AI summary
A semiconductor device includes one or more first transistors of which each source connects to a power wiring, a second transistor of which a source connects to a ground wiring and a drain connects to a drain of the first transistor, one or more third transistors of which each source connects to the power wiring and each drain connects to the drains of the first and second transistors, and a gate potential control circuit which controls the gate potential of the third transistors based on the potential of the power wiring.