Semiconductor Device Surge Tolerance via Penetrating Diffusion Regions
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing surge tolerance while maintaining size reduction and cost efficiency, particularly in high-side power ICs, where the parasitic bipolar element in the circuit portion tends to snap back, leading to reduced breakdown current and increased risk of breakdown, especially when the footprint of components is minimized.
Innovation Solution
The semiconductor device incorporates a protective element with a higher operation resistance vertical diode, featuring a p+-type diffusion region that penetrates the p−-type diffusion region in the depth direction and includes an n+-type diffusion region between the p+-type and p++-type contact regions, allowing the protective element to absorb surge current effectively and prevent snapback in the circuit portion, even when the contact hole width is reduced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the footprint of components is minimized to reduce device size, then device size is reduced, but surge tolerance deteriorates due to increased snapback risk in parasitic bipolar elements
Solution Approach 1:
A protective element is introduced as an intermediary component between the power supply terminal and ground terminal. This protective element includes a vertical diode with specifically designed p-type and n-type diffusion regions that act as a mediator to suppress snapback in the parasitic bipolar element, thereby maintaining surge tolerance even when the device footprint is minimized.
Solution Approach 2:
The protective element employs non-uniform impurity concentration distribution with different doping levels in different regions. The p-type diffusion region has a first impurity concentration while the n-type diffusion region has a second impurity concentration, creating local quality variations that optimize both the snapback suppression capability and the overall device size.
2Reliability
If a protective element is added to enhance surge tolerance, then reliability is improved, but device complexity increases
Solution Approach 1:
The protective element is merged with the existing semiconductor structure by integrating the vertical diode into the power supply terminal region. The p-type diffusion region is formed in conjunction with existing structures, and the n-type diffusion region is selectively provided to overlap with the p-type region, combining multiple functions into a unified structure that enhances surge tolerance without proportionally increasing complexity.
Solution Approach 2:
The protective element serves multiple functions: it acts as a vertical diode for surge protection, provides snapback suppression through its specific diffusion region configuration, and maintains compatibility with existing device architectures. This multi-functionality allows a single structure to address multiple reliability concerns without requiring separate dedicated components for each function.
3Productivity
If contact hole width is reduced to increase integration density, then productivity is improved, but manufacturing precision requirements worsen due to increased risk of breakdown
Solution Approach 1:
The protective element with its specifically designed diffusion regions provides beforehand cushioning against potential breakdown risks. The p-type diffusion region with first impurity concentration and the overlapping n-type diffusion region with second impurity concentration create a buffered structure that prevents direct exposure of the contact hole to high-stress conditions, thereby reducing the precision requirements for contact hole formation and alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the surge tolerance of the power IC by suppressing surge current concentration at the contact portion and maintaining stable protection against process variations, while allowing for size reductions and cost-effective manufacturing.
Implementation Method 1
a p+-type diffusion region that penetrates the p−-type diffusion region in the depth direction
Implementation Method 2
a higher operation resistance vertical diode, featuring a p+-type diffusion region that penetrates the p−-type diffusion region
Data Source
AI summary
In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.