Semiconductor Device With Surrounding Gate Transistors
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Solution Overview
Problem
The increasing integration of transistors in semiconductor chips leads to challenges in minimizing chip area, as traditional planar transistors require separate n-well and p-well regions for isolation and body terminals, which increases the chip area and complexity.
Innovation Solution
The use of surrounding gate transistors (SGTs) with a silicon pillar structure eliminates the need for well isolation and body terminals, allowing for a compact layout by arranging six transistors in a line with connected gates and address signal lines perpendicular to the substrate, reducing the overall area required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar transistors are used with separate n-well and p-well regions, then transistor isolation is achieved, but chip area increases due to required body terminals and isolation structures
Solution Approach 1:
The patent merges the isolation function and body terminal function into a single shared substrate potential structure. By using a common substrate potential for both n-well and p-well regions, the invention eliminates the need for separate body terminals while maintaining proper transistor isolation, thereby reducing chip area.
Solution Approach 2:
The substrate potential structure serves multiple functions simultaneously: it provides electrical isolation between n-channel and p-channel transistors, acts as a common body terminal for both transistor types, and establishes proper potential references. This multi-functionality eliminates redundant structures and reduces overall chip area.
2Reliability
If traditional planar transistors with complete well isolation are used, then transistor performance is maintained, but device complexity increases due to additional isolation structures and body terminals
Solution Approach 1:
The patent extracts and eliminates the redundant body terminal structures from the traditional planar transistor design. By removing the separate body terminals for n-well and p-well regions and replacing them with a shared substrate potential, the invention maintains transistor performance while significantly reducing structural complexity.
Solution Approach 2:
The invention combines the body terminal functions of n-well and p-well transistors into a single shared substrate potential structure. This merging eliminates the need for separate body terminal connections and associated isolation structures, thereby reducing device complexity while maintaining proper transistor operation.
3Area of stationary object
If six transistors are arranged in a line with connected gates and perpendicular address signal lines, then area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from a traditional planar arrangement to a three-dimensional structure where transistor gates are connected vertically through multiple layers. By stacking transistors and connecting gates in the vertical dimension, the invention achieves compact lateral area while distributing alignment requirements across multiple fabrication layers, thereby managing manufacturing precision challenges.
Data Source
AI summary
A semiconductor device includes a 3-input NAND decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.