Semiconductor Switch Cell Layout Using Global Metal Lines
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Solution Overview
Problem
The dense placement of switch cells to supply virtual voltage and ground voltage to standard cells in semiconductor devices increases area complexity and reduces performance due to intricate interconnections.
Innovation Solution
A layout design for semiconductor devices that includes strategically placed switch cells with overlapping global metal lines to simplify power and ground voltage supply paths, minimizing interconnections and enhancing routing effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switch cells are densely placed to supply virtual voltage and ground voltage to standard cells, then the power supply capability is improved, but the area increases and interconnections become complicated
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture by placing switch cells at different vertical levels (first level and second level) on the substrate. This vertical stacking enables power supply to multiple standard cells without increasing horizontal area, and the global metal lines can serve multiple switch cells simultaneously, reducing interconnection complexity.
Solution Approach 2:
The global metal lines are designed to extend in the first direction and overlap multiple switch cells in plan view, enabling a single global metal line to supply power to multiple switch cells. This multi-functional design reduces the total number of interconnections needed compared to dedicated point-to-point connections.
2Reliability
If switch cells are densely placed to supply virtual voltage and ground voltage to standard cells, then the power supply capability is improved, but the area occupied by switch cells increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking switch cells at different levels (first level and second level) on the substrate. This allows the same horizontal area to accommodate multiple switch cells vertically, significantly increasing power supply capability without proportionally increasing the occupied area.
Solution Approach 2:
The patent implements a nested structure where switch cells are vertically stacked and interconnected through vertical vias, with global metal lines extending horizontally to serve multiple nested switch cells. This nesting approach maximizes the use of vertical space while maintaining efficient power distribution.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first switch and second switch cells that are disposed on a substrate and spaced apart from each other; a first metal line that is electrically connected to the first switch cell; a second metal line that is electrically connected to the second switch cell; a third metal line that is interposed between the first metal line and the second metal line; a first global metal line that at least partially overlaps the first switch cell and the second switch cell in a plan view, and electrically connects the first metal line and the second metal line; and a second global metal line that is adjacent to the first global metal line in the plan view, and is electrically connected to the third metal line.