Semiconductor Switch Device with Isolation Regions for RF MOSFETs
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Solution Overview
Problem
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) used as RF switches face challenges in achieving low off-state capacitance without increasing on-state resistance, as parasitic junction capacitances contribute significantly to total off-state capacitance.
Innovation Solution
Incorporating isolation regions between electrical contacts on the source and drain regions, which extend through the substrate, reduces parasitic junction capacitance while maintaining similar on-state resistance by optimizing contact size and layout to facilitate current spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate contacts are used instead of a monolithic contact to accommodate isolation regions, then parasitic junction capacitance is reduced, but device complexity increases
Solution Approach 1:
The contact structure is segmented into multiple smaller contacts that can be arranged in a systematic pattern. This segmentation, combined with the regular placement of isolation regions between contacts, creates a modular structure that reduces parasitic capacitance while maintaining manufacturing feasibility through standardized fabrication processes
Data Source
AI summary
A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.