High Frequency Semiconductor Switch Off-Capacitance Reduction

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Solution Overview

Problem

High frequency semiconductor switches with multi-port configurations experience increased off-capacitance and insertion loss due to the number of through FET groups in the non-conductive state, leading to distortion current issues when voltage is applied to through FET groups in a non-conductive state.

Innovation Solution

A dual-step structure is implemented with a first through FET group and multiple second through FET groups, where the number of MOSFETs in each group is selected to maintain voltages below breakdown voltages, and a shunt FET group is connected between second terminals and a ground, reducing off-capacitance and insertion loss by serially connecting through FET groups and using fully-depleted MOSFETs on an SOI substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of ports is increased in an SPnT switch, then the communication frequency band and number of communication standards are addressed, but the off-capacitance increases and insertion loss increases

Engineering Contradiction:

Improvecommunication frequency band coverageVSAvoidinsertion loss

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The through FET groups are divided into a first through FET group and multiple second through FET groups with different numbers of FETs. This segmentation allows voltage distribution across groups, reducing off-capacitance effects and insertion loss while maintaining multi-port functionality for various communication standards

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If a common through FET group is connected to through FET groups to decrease off-capacitance, then off-capacitance is reduced, but the voltage between source and drain of FETs in the common group becomes high, resulting in increasing distortion current

Engineering Contradiction:

Improveoff-capacitanceVSAvoiddistortion current

Core Design Contradiction:

Loss of energyVSObject-generated harmful factors

Solution Approach 1:

Different through FET groups are designed with different numbers of FETs based on their specific port requirements. The first through FET group has a different number of FETs compared to the second through FET groups, allowing each group to handle voltage appropriately and prevent excessive voltage that would cause distortion current

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If the number of through FET groups in non-conductive state is increased, then more ports are provided for multi-port configuration, but the off-capacitance increases leading to increased distortion current

Engineering Contradiction:

Improvenumber of portsVSAvoiddistortion current

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The through FET groups are segmented into different categories (first and second groups) with different FET counts. This segmentation ensures that even when multiple groups are in non-conductive state, the off-capacitance is controlled and distortion current is minimized by having groups with fewer FETs in the non-conductive state

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The number of FETs in each through FET group is changed as a parameter to control off-capacitance characteristics. By having the first through FET group with a different number of FETs compared to second through FET groups, the patent optimizes the balance between multi-port capability and distortion current suppression

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dual-step structure significantly decreases off-capacitance and insertion loss, suppressing distortion to desired levels while maintaining acceptable on-resistances, thereby improving the performance of high frequency semiconductor switches in wireless devices.

Implementation Method 1

using fully-depleted MOSFETs on an SOI substrate

Methodology Applied

Scientific EffectDepletion region formation:

Implementation Method 2

MOSFETs formed on an SOI (Silicon On Insulator) substrate

Methodology Applied

Scientific EffectSOI substrate effect:

Implementation Method 3

the number of MOSFETs in each group is selected to maintain voltages below breakdown voltages

Methodology Applied

Scientific EffectVoltage distribution in series connection:

Data Source

PatentUS9461643B2High freuency semiconductor switch and wireless device

Publication Date: 2016.10.04 KK TOSHIBA

AI summary

A high frequency semiconductor switch has a first terminal, second terminals, a first through FET group, second through FET groups and a shunt FET group. The first through FET group has first field effect transistors connected serially with each other. One end of the first through FET group is connected to the first terminal. Each of the second through FET groups has second field effect transistors connected serially with each other. One end of each of the second through FET groups is connected to each of the second terminals. The other end of each of the second through FET groups is commonly connected to the other end of the first through FET group. The shunt FET group has third field effect transistors connected serially with each other between the second terminal and a ground terminal.