Semiconductor Etching Using Symmetric Mask Patterns
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Solution Overview
Problem
The manufacturing of highly integrated semiconductor devices faces challenges in forming minute patterns with critical dimensions of several nanometers to tens of nanometers, requiring innovative methods to achieve precise and uniform feature formation.
Innovation Solution
The method involves forming sacrificial layer patterns, conformal mask layers, and symmetric mask patterns to enable precise etching of target layer patterns, ensuring uniformity and minimal variations in pattern width and height, using techniques such as anisotropic etching and plasma ashing or isotropic etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography and etching methods are used, then manufacturing process is simple, but manufacturing precision of minute patterns deteriorates
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming sacrificial layer patterns, depositing first and second mask layers, selective etching to form preliminary mask patterns, filling spaces, and final etching. This segmentation allows each stage to be optimized independently for precision while maintaining overall process manageability
Solution Approach 2:
Sacrificial layer patterns are formed in advance before the actual mask patterns are created. These preliminary sacrificial structures serve as templates that guide subsequent mask formation and ensure precise pattern transfer to the target layer, achieving high manufacturing precision through preparatory structuring
2Productivity
If minute patterns with critical dimension of several nanometers are formed, then device integration is improved, but manufacturing precision deteriorates due to process variations
Solution Approach 1:
Different mask layers are used at different locations and stages: the first mask layer forms preliminary patterns with specific width characteristics, while the second mask layer refines these patterns with different etching selectivity. This local differentiation of mask properties ensures consistent pattern width uniformity across the entire structure despite variations at the nanometer scale
Solution Approach 2:
The method employs composite masking structures consisting of multiple mask layers with different material compositions and etching characteristics. This composite approach allows optimization of each layer's properties to compensate for process variations, maintaining high manufacturing precision in highly integrated devices
3Manufacturing precision
If multiple etching steps are performed, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The etching process is designed as a continuous sequence where the first mask layer is etched, then immediately replaced by a second mask layer for further etching without breaking the process flow. This continuous action minimizes idle time between steps while maintaining the precision benefits of multiple etching stages
Solution Approach 2:
Multiple mask formation and etching operations are merged into an integrated process sequence where sacrificial layer removal, mask deposition, and etching steps are combined efficiently. The filling step merges space occupation with pattern definition, reducing the number of separate operations needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of semiconductor devices with uniform and precise target layer patterns, minimizing width variations and height differences, which is crucial for highly integrated semiconductor manufacturing.
Implementation Method 1
conformally forming a mask layer on the sacrificial layer pattern and the etch target
Implementation Method 2
conformally forming a mask layer on the sacrificial layer pattern and the etch target
Implementation Method 3
anisotropically etching the connecting portion of each of the mask patterns and the etch target to form a plurality of target layer patterns
Implementation Method 4
using techniques such as anisotropic etching and plasma ashing or isotropic etching processes
Data Source
AI summary
In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.