Tab Design for Semiconductor Devices to Prevent Sealing Cracks
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Solution Overview
Problem
Tab-exposed-type semiconductor devices experience reliability degradation due to cracks in the sealing body, particularly in the vicinity of the thinner region, which allows moisture ingress and reduces the device's reliability over time.
Innovation Solution
The semiconductor device features a tab with a thinner region that is sealed within the sealing body, incorporating protruding and recessed portions to distribute stress and prevent crack formation, and an adhesive material that forms a fillet to enhance adhesion, thereby reducing stress concentration and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the tab is provided with a thinner region to be sealed in the sealing body to prevent the tab from falling out, then the tab retention is improved, but cracks occur in the sealing body particularly in the vicinity of the thinner region due to stress concentration under temperature cycles
Solution Approach 1:
The patent applies local quality by providing protruding portions and recessed portions at specific locations on the tab. These structural features create localized stress distribution patterns that prevent crack formation in the sealing body while maintaining the thinner region's ability to retain the tab. The protruding and recessed portions are strategically positioned to alter the stress field locally without changing the overall tab structure.
Solution Approach 2:
The tab is segmented into multiple regions including protruding portions and recessed portions. This segmentation divides the continuous tab structure into distinct functional zones that can independently manage stress distribution. The protruding portions extend from the tab surface while recessed portions create indentations, effectively segmenting the stress path and preventing crack propagation through the sealing body.
2Ease of manufacture
If the outer edge of the semiconductor chip is located between the first and second portions of the chip mounting portion, then the chip mounting structure is optimized, but stress concentration occurs in the sealing body leading to crack formation
Solution Approach 1:
The patent modifies the local geometry of the chip mounting portion by adding protruding and recessed portions. These local structural changes create favorable stress distribution zones that prevent crack formation while maintaining the optimized chip mounting configuration. The protruding portions provide additional support areas, and the recessed portions create stress relief zones near the chip edges.
Solution Approach 2:
The protruding and recessed portions are designed in advance to cushion against stress concentration before cracks can form. These features act as preventive measures that distribute thermal and mechanical stresses away from critical areas during temperature cycling, thereby protecting the sealing body integrity before damage occurs.
3Strength
If adhesive material is disposed between the semiconductor chip and the thinner region to enhance adhesion, then the chip bonding strength is improved, but the adhesive forms a fillet that concentrates stress in the sealing body
Solution Approach 1:
The patent addresses the adhesive-related stress concentration by introducing protruding and recessed portions that locally modify the stress distribution. These features create zones of reduced stress near the adhesive fillet, allowing the adhesive to maintain strong bonding while preventing the fillet from becoming a crack initiation site in the sealing body.
Solution Approach 2:
The adhesive bonding interface is effectively segmented by the protruding and recessed portions. These features divide the continuous adhesive layer into multiple zones with different stress characteristics, preventing the formation of a large concentrated stress region at the adhesive fillet while maintaining overall bonding strength.
Data Source
AI summary
A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.