Semiconductor Device Tap Region Leak Current Reduction
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Solution Overview
Problem
Leak current in the tap region of semiconductor devices with SRAM memory cells having a thin-film BOX-SOI structure leads to increased power consumption, making it difficult to reduce energy efficiency.
Innovation Solution
The semiconductor device incorporates an n-type well region, element isolation region, and a dummy gate electrode layer that is electrically floating, with power supply wirings coupled to n-type and p-type well regions, reducing through-currents and power consumption by managing transistor thresholds during standby and operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gate electrode layers are disposed in the tap region and coupled with power supply wirings, then the structure provides proper potential supply to well regions, but leak current occurs in the tap region area where dummy gate electrode layers are located, increasing power consumption
Solution Approach 1:
The patent extracts the dummy gate electrode layers from the tap region to eliminate the source of leak current. By removing these unnecessary gate structures from areas where memory cells are not disposed, the patent prevents the generation of leak current while maintaining proper potential supply to well regions through alternative means.
Solution Approach 2:
The patent applies different structural qualities to different regions: in the tap region where no memory cells are disposed, dummy gate electrode layers are eliminated to prevent leak current, while in memory cell regions, proper gate electrode structures are maintained to ensure correct transistor operation. This localized structural differentiation resolves the contradiction between reliable potential supply and power consumption.
2Productivity
If SRAM memory cells are arranged in matrix pattern over semiconductor substrate, then memory array functionality is achieved, but tap regions require power supply wirings that extend through the structure, creating pathways for leak current
Solution Approach 1:
The patent segments the semiconductor device into distinct functional regions: memory cell regions with full transistor structures and tap regions for power supply. By properly managing the boundaries and structures in tap regions, the patent prevents leak current pathways while maintaining the segmented architecture necessary for memory array functionality.
Data Source
AI summary
A semiconductor device, includes: a semiconductor substrate having a first well region; an insulating layer formed on a first portion of the semiconductor substrate, and contacted with the first well region; a semiconductor layer formed on the insulating layer; an element isolation region reaching to an inside of the first well region, in cross-section view; a first gate electrode layer formed on a first portion of the semiconductor layer via a first gate insulating film; a second gate electrode layer formed on a second portion of the semiconductor layer via a second gate insulating film, and formed on a first portion of the element isolation region; an interlayer insulating film covering the first gate electrode layer, the second gate electrode layer and a second portion of the element isolation region; and a first plug conductor layer formed in the interlayer insulating film.