Semiconductor Package Tapered Bumps Wiring Density
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Solution Overview
Problem
The existing semiconductor packages face challenges in increasing the density of wiring patterns due to the small gap between bumps formed on semiconductor devices with different thicknesses, limiting the number of wiring patterns that can be led through the gap between exposed surfaces.
Innovation Solution
The semiconductor package involves fixing semiconductor devices with different thicknesses to a support plate such that terminal surfaces are level, forming tapered bumps on the electrode terminals to penetrate an insulating layer, and connecting a wiring pattern to the exposed tip surface of these bumps, which allows for a higher density of wiring patterns by increasing the gap between bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bumps with almost equal diameter to electrode terminals are formed on semiconductor devices with different thicknesses to make tip surfaces level, then manufacturing feasibility is improved, but the gap between exposed bump surfaces becomes small, making it difficult to form fine wiring patterns and increasing device complexity
Solution Approach 1:
The patent applies asymmetry by forming bumps with different diameters than the electrode terminals they connect to. Specifically, the bumps have a smaller diameter than the electrode terminals, creating an asymmetric geometry that allows the bump tip surface to be smaller than the terminal surface. This asymmetric design enables the bump tip to be exposed at a lower level than adjacent bumps, thereby increasing the gap between exposed bump surfaces and allowing for finer wiring patterns to be formed in the spaces between them.
2Productivity
If electrode terminal density is increased with reduced semiconductor device sizes, then device miniaturization is improved, but the gap between adjacent bumps becomes small, limiting the number of wiring patterns that can be led through the gaps
Solution Approach 1:
The asymmetric bump design where bump diameter is smaller than electrode terminal diameter creates exposed tip surfaces that are smaller than the terminal surfaces. This asymmetry increases the vertical gap between exposed bump tips, providing more space for wiring patterns even when electrode terminals are densely packed in miniaturized devices.
Solution Approach 2:
The patent utilizes the vertical dimension by creating level differences between bump tip surfaces. Instead of relying solely on horizontal spacing between bumps, the invention introduces a vertical dimension to the gap structure by having bumps at different exposure levels, thereby creating three-dimensional wiring space that accommodates more wiring patterns in densely packed devices.
Data Source
AI summary
A plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals are fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other. An insulating layer covers terminal forming surfaces of the semiconductor devices. At least one tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal of the semiconductor device is formed on one of the terminal surfaces of the electrode terminals and penetrates the insulating layer in such a manner that the tip surface of the tapered bump is exposed to a surface of the insulating layer. A wiring pattern is formed on the surface of the insulating layer and connected to the tip surface of the tapered bump.