Patterned Conductive Landing Pads for Semiconductor TEG Testing
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Solution Overview
Problem
As semiconductor memory devices become smaller, the challenges in assessing the electric properties of elements on the chip increase, particularly due to the reduced line width, which complicates the testing of semiconductor memory devices using test element groups (TEG) formed on scribe lines.
Innovation Solution
A method of manufacturing a semiconductor structure involves forming a conductive layer with patterned landing pads in a test group region, where these pads are electrically connected through contact plugs and transistors, allowing for effective testing of the semiconductor structure by ensuring proper formation and connection of elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the line width in semiconductor memory devices is reduced to make products lightweight and compact, then the integration of functional devices increases, but semiconductor process techniques face many challenges in testing and assessment
Solution Approach 1:
The patent segments the testing function by separating the TEG formation from the main chip area and placing it in the scribe line region. This allows independent testing of transistor elements without affecting the main memory device functionality, making it easier to assess electric properties in miniaturized devices.
Solution Approach 2:
The patent introduces an intermediary conductive layer with specific patterned landing pads that connects external testing equipment to the TEG elements. This intermediary structure facilitates measurement by providing accessible test points while isolating the testing process from the main device operation.
2Productivity
If test element groups are formed on scribe line areas to assess electric properties, then the number of semiconductor memory devices produced from the wafer is maximized, but the complexity of forming and connecting test structures increases
Solution Approach 1:
The patent merges the TEG formation process with the existing semiconductor manufacturing process steps. The conductive layer is formed using the same process as for the memory devices, and the TEG structures are integrated into the scribe line area, combining testing functionality with the production flow to reduce overall complexity.
Solution Approach 2:
The conductive layer serves multiple functions: it acts as both the interconnect for the memory devices and the test structure for the TEG. The same conductive material and formation process are used for both functional and testing purposes, reducing the number of additional structures needed.
3Measurement precision
If the conductive layer is patterned to form separated landing pads that are electrically connected through contact plugs and transistors, then accurate testing of semiconductor memory devices is enabled, but the manufacturing process steps increase
Solution Approach 1:
The patent performs preliminary patterning of the conductive layer to form the landing pad structure before final connection establishment. The conductive layer is first patterned with landing pads in the TEG region, then contact plugs are formed to connect these pads to the transistor elements, preparing the structure for accurate testing while managing process complexity.
Solution Approach 2:
The patent uses vertical stacking in the third dimension to achieve electrical connections. Contact plugs extend vertically through the interlayer dielectric to connect the patterned conductive layer landing pads to the transistor source/drain regions, enabling three-dimensional integration that simplifies the overall manufacturing compared to planar routing.
Data Source
AI summary
A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.