Semiconductor Temperature Sensor with Synchronized Latch Circuits
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Solution Overview
Problem
Semiconductor devices, such as DRAM, face challenges in accurately measuring chip temperatures for effective operations of various circuits, as existing temperature sensors may not provide timely and precise temperature data, affecting refresh control and overall performance.
Innovation Solution
A semiconductor device configuration that includes a detection signal generator with a temperature sensor synchronized with a cyclic oscillation signal, utilizing latch circuits and a selector to ensure accurate and timely temperature measurement, preventing overlapping latching actions that could result in undefined detection signals, and outputting a 3-bit sense signal for precise temperature data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a temperature sensor is integrated into the semiconductor device, then temperature measurement capability is improved, but device complexity increases
Solution Approach 1:
The patent combines the temperature sensor with the existing oscillation signal generation circuitry within the semiconductor device. The temperature sensor is integrated into the oscillator circuit, allowing temperature measurement functionality to be merged with the existing timing/clock generation functions, thereby reducing overall device complexity while maintaining measurement precision.
Solution Approach 2:
The oscillation signal generator serves dual purposes: it generates clock/timing signals for device operation and simultaneously drives the temperature sensor for measurement. This multi-functionality eliminates the need for separate dedicated temperature sensing circuitry, reducing device complexity while maintaining accurate temperature measurement capability.
2Loss of time
If latch circuits are used to capture temperature data, then measurement timing precision is improved, but device complexity increases
Solution Approach 1:
The latch circuits are integrated into the existing data output circuitry of the semiconductor device. The same latching mechanism used for capturing other operational data is also employed to capture temperature sensor readings at precise moments, eliminating the need for separate dedicated latching circuitry for temperature data.
Solution Approach 2:
The temperature measurement and data capture occur periodically synchronized with the oscillation signal cycles. By using the periodic oscillation signal to trigger measurements and latch operations at specific phases, the system achieves precise timing control without requiring complex continuous monitoring circuitry.
3Loss of information
If the temperature sensor operates continuously, then temperature data availability is improved, but energy consumption increases
Solution Approach 1:
The temperature sensor operates periodically rather than continuously, synchronized with the oscillation signal cycles. Measurements are taken at specific phases of the oscillation cycle, and the sensor is placed in a low-power state between measurements. This periodic operation ensures temperature data is available at critical moments while significantly reducing overall energy consumption compared to continuous operation.
Solution Approach 2:
The temperature sensor utilizes the existing oscillation signal and power management circuitry of the semiconductor device for its operation. The sensor is powered and controlled by the same clock/oscillation signals that drive other device functions, eliminating the need for separate power management circuitry and reducing overall energy consumption.
Data Source
AI summary
Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.