Semiconductor Device Tensile Stress Base Region
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing ON-resistance while maintaining breakdown voltage, as existing designs do not effectively distribute tensile stress across the semiconductor regions to enhance carrier mobility.
Innovation Solution
The semiconductor device incorporates a second insulating part positioned between the n−-type drift region and the contact part, arranged perpendicular to the first insulating part, to increase tensile stress in the p-type base region, thereby reducing ON-resistance and suppressing parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tensile stress is increased in the base region to enhance carrier mobility, then ON-resistance decreases, but device complexity increases
Solution Approach 1:
Tensile stress is applied locally only to specific portions of the base region where carriers need enhanced mobility, rather than uniformly across the entire device. The insulating part is positioned to create stress only in the base region segments between source regions, leaving other areas unchanged
Solution Approach 2:
The insulating part extends in the third dimension (vertical direction) between the drift region and source regions, creating stress through its physical presence and dimensional occupation rather than through complex in-plane structural modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces ON-resistance by increasing tensile strain in the p-type base region, while maintaining or improving breakdown voltage, and enhances carrier mobility, thus improving the overall performance of the semiconductor device.
Implementation Method 1
increase tensile stress in the p-type base region, thereby reducing ON-resistance and suppressing parasitic transistor operation
Data Source
AI summary
According to one embodiment, a semiconductor device includes first to third electrodes, first to third semiconductor regions, first and second insulating parts, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor regions are provided selectively on the second semiconductor region. The first insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The second electrode is provided inside the first insulating part. The gate electrode is provided inside the first insulating part and electrically isolated from the second electrode. The third electrode is provided on the second and third semiconductor regions. The third electrode includes a contact part provided between the third semiconductor regions. The second insulating part is provided between the first semiconductor region and the contact part.