Semiconductor Terminal Arrangement for Test Contact and Thermal Stress
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Solution Overview
Problem
The increasing number of terminals in semiconductor devices for testing poses a challenge as they are often difficult to contact due to their arrangement among external wiring terminals, leading to reduced user-accessible surface area on the mounting substrate and increased stress from thermal expansion.
Innovation Solution
A semiconductor device design where first terminals without metal balls are arranged closely together, and second terminals with metal balls surround them, allowing for increased test terminals while maintaining user-accessible area and reducing thermal expansion stress by positioning the second terminals away from the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If test terminals are arranged among external wiring terminals in a lattice form, then the number of test terminals can be increased, but it becomes difficult to contact the test terminals to terminals of a test tool
Solution Approach 1:
The patent divides the terminal arrangement into distinct groups: first terminals (external wiring terminals) arranged in a lattice form for user connections, and second terminals (test terminals) arranged in a separate test terminal arrangement area. This segmentation allows test terminals to be grouped together rather than dispersed among external terminals, making them easier to contact while still increasing the overall number of test terminals available.
2Ease of operation
If test terminals are centralized in a separate area, then contact to test terminals becomes easier, but the user has less opening area on the surface of the mounting substrate for wiring
Solution Approach 1:
The patent extends the terminal arrangement in multiple directions by arranging first terminals in a lattice form that can extend beyond the test terminal arrangement area in at least one direction. This dimensional expansion allows the external wiring terminals to utilize space in directions away from the centralized test terminal area, effectively increasing the available opening area for user wiring while maintaining easy access to test terminals.
3Reliability
If second terminals are positioned near the semiconductor chip, then electrical connection is achieved, but stress from thermal expansion increases
Solution Approach 1:
The patent introduces a land pattern as an intermediary element between the second terminals (test terminals) and the semiconductor chip. This land pattern serves as a buffer zone that decouples the thermal expansion stress from the test terminals while maintaining the necessary electrical connection path. The intermediary structure allows thermal expansion to occur without directly transmitting stress to the test terminals.
Data Source
AI summary
A semiconductor device includes a semiconductor chip and a wiring substrate. The wiring substrate is configured to be electrically connected to the semiconductor chip, and have a plurality of terminals arranged on an surface opposite to a surface on which the semiconductor chip is mounted. The plurality of terminals includes a plurality of first terminals configured to be arranged closely to each other, and a plurality of second terminals configured to be arranged so as to surround the plurality of first terminals. The plurality of second terminals is provided such that terminals of the semiconductor chip are connected to outer terminals through the plurality of second terminals. Each of the plurality of first terminals is not provided with a metal ball, while each of the plurality of second terminals is provided with a metal ball.