Semiconductor Terminal Engagement Structure for Low-Inductance Assembly

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Solution Overview

Problem

Conventional power semiconductor modules lack a configuration that ensures accurate positioning of multiple terminals due to assembly tolerance, leading to inefficiencies in wire inductance reduction and manufacturing precision.

Innovation Solution

A semiconductor device configuration featuring insulated circuit substrates, semiconductor chips, external terminals, and insulating members with engagement parts and sealing resin, which ensures accurate positioning of terminals through integrated structure bodies and reduced wire inductance, eliminating the need for external casings and simplifying manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional power semiconductor modules are assembled without special positioning configurations, then assembly process is simple, but terminal positioning accuracy is insufficient due to assembly tolerance

Engineering Contradiction:
Improveterminal positioning accuracyVSAvoidassembly structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulating members are provided with engagement parts (protrusions and recesses) in advance during manufacturing, which automatically guide and position the terminals during assembly. This preliminary preparation of positioning features eliminates the need for complex external positioning fixtures while ensuring accurate terminal alignment, directly resolving the contradiction between positioning accuracy and assembly simplicity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The engagement parts on the insulating members enable the terminals to self-position and self-align during assembly through the protrusion-recess mechanism. The structure automatically compensates for assembly tolerances without requiring external positioning devices or complex assembly procedures, thereby achieving high positioning accuracy while maintaining simple assembly process

Inventive Principle:
Principle #25Self-service

2Loss of energy

If terminals are arranged adjacently to reduce wire inductance, then wire inductance decreases, but positioning accuracy becomes more difficult to ensure due to tolerance accumulation

Engineering Contradiction:
Improvewire inductanceVSAvoidterminal positioning accuracy
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The engagement parts are pre-formed on the insulating members with precise dimensions and positions. When terminals are arranged adjacently, these pre-formed engagement parts maintain consistent spacing and alignment, preventing tolerance accumulation even in compact arrangements. This enables both low inductance through adjacent terminal placement and high positioning accuracy through the pre-prepared positioning features

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The insulating members act as intermediary elements between adjacent terminals, with their engagement parts providing precise positioning references. This intermediary structure eliminates direct contact between terminals while maintaining accurate relative positioning, allowing adjacent arrangement for low inductance without sacrificing positioning accuracy

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250014981A1Semiconductor device
Publication Date: 2025.01.09 FUJI ELECTRIC CO LTD
  • US20250014981A1 patent drawing
  • US20250014981A1 patent drawing
  • US20250014981A1 patent drawing

AI summary

A semiconductor device includes: an insulated circuit substrate including an insulating plate and a conductive plate provided on a top surface side of the insulating plate; a semiconductor chip provided on a top surface side of the conductive plate; a first external terminal electrically connected to the semiconductor chip; a first insulating member including a covering part covering a part of the first external terminal and a first engagement part provided on a top surface side of the covering part; a second external terminal provided on a top surface side of the first external terminal with the covering part interposed, and including a second engagement part so as to engage with the first engagement part; and a sealing resin provided to seal the semiconductor chip and partly seal each of the first external terminal, the first insulating member, and the second external terminal.