Semiconductor Terminal Fault Detection with Normalized Delay Comparison
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Solution Overview
Problem
There is a demand for more accurate and reliable mechanisms to detect faults at the terminals of semiconductor arrangements, particularly in critical applications like automotive motor control, where terminal failures can lead to incorrect signal transmission and system failure.
Innovation Solution
A semiconductor arrangement with a monitoring system that compares measures of delay for signals across multiple terminals to detect faults, using techniques such as Schmitt triggers and diodes to analyze delay variations and account for temperature and supply voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault detection methods are used at semiconductor terminals, then the system structure remains simple, but the accuracy and reliability of fault detection deteriorates
Solution Approach 1:
The semiconductor arrangement monitors its own terminal faults using integrated signal generators and delay measurement circuits built into the device itself, eliminating the need for external monitoring equipment and improving detection reliability without proportionally increasing overall system complexity
Solution Approach 2:
The patent replaces complex electrical fault detection mechanisms with a timing-based delay measurement approach, where voltage transitions are measured and compared to detect terminal faults, simplifying the monitoring system while improving detection accuracy
2Measurement precision
If delay measurements are taken without normalization, then the measurement process is simple, but measurement precision deteriorates due to temperature and voltage fluctuations
Solution Approach 1:
The patent measures delay at multiple specific voltage thresholds (e.g., 25% and 75% of VDD) and normalizes these measurements to account for temperature and voltage variations, transforming raw delay values into standardized metrics that maintain precision across different operating conditions
Solution Approach 2:
The system continuously monitors delay variations and compares them against normalized reference values, using feedback mechanisms to detect anomalies that indicate terminal faults, thereby maintaining high measurement precision through adaptive comparison
3Reliability
If multiple delay measurements are compared to detect faults, then fault detection accuracy improves, but the time required for measurement and analysis increases
Solution Approach 1:
The patent performs delay measurements at multiple voltage thresholds simultaneously in a coordinated manner, with the signal generator providing test signals that are evaluated across different voltage points in sequence, reducing total measurement time while maintaining high accuracy through parallel evaluation of multiple parameters
Data Source
AI summary
A mechanism for predicting the occurrence of a fault at a terminal of a semiconductor arrangement is provided. A measure of delay is obtained for each of a plurality of terminals of the semiconductor arrangement. The measures of delay are compared to one another to predict whether or not there is a fault at a terminal of the semiconductor arrangement.