Semiconductor Device Terminal Grouping for Short Circuit Mitigation
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Solution Overview
Problem
The manufacturing cost of semiconductor devices is increased due to the need for multiple redundant lines and complex testing processes to address failures in inter-chip signal paths caused by improper microbump bonding, which can lead to short circuits and open circuits.
Innovation Solution
The semiconductor device is designed with terminals divided into multiple redundant groups, where each group has terminals placed at larger intervals, reducing the probability of short circuits and simplifying the testing process by executing tests for each redundant group, thereby reducing the circuit size and testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple redundant lines are used to bypass failed signal paths, then the reliability of inter-chip connections is improved, but the device complexity and manufacturing cost are increased
Solution Approach 1:
The invention divides terminals into multiple redundant groups (first redundant group, second redundant group, etc.) where each group contains terminals that can serve as backups for others. This segmentation allows the system to handle failures in a structured way, reducing the overall complexity compared to having individual backup paths for each terminal while maintaining reliable inter-chip connections.
2Productivity
If terminals are placed at shorter intervals to increase I/O density, then the data transmission rate is improved, but the probability of short circuits between adjacent lines is increased
Solution Approach 1:
The invention applies different spatial arrangements to different groups of terminals. Terminals within the same redundant group are placed at larger intervals to reduce short circuit probability, while terminals in different groups can be densely packed to maximize I/O density. This local differentiation of spatial quality allows the system to achieve high data transmission rates while mitigating short circuit risks through strategic terminal placement.
3Productivity
If the number of microbumps is increased to place more I/O terminals, then the bus width is widened and data transmission rate is improved, but the test time and manufacturing cost are increased
Solution Approach 1:
The invention merges the testing of multiple terminals into group-level testing. By organizing terminals into redundant groups and testing each group as a unit rather than individually, the system reduces test time while maintaining comprehensive coverage. This combining approach allows for efficient verification of inter-chip connections even when many microbumps and I/O terminals are used.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A semiconductor device includes chips, wherein a first chip includes: an internal circuit (CKT1); first selectors (SELU1) to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units (OBU1, OBU2, OBU3) to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals (TM10a, TM12a, TM14a) to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals (TM13b, TM15b) to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances smaller than the first distances.