Semiconductor Terminal Guard Ring for Avalanche Breakdown
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Solution Overview
Problem
High breakdown voltage semiconductor devices, such as IGBTs and MOSFETs, face issues with avalanche breakdown at the terminal parts due to insufficient carrier removal, leading to electric field concentration and potential device failure.
Innovation Solution
The semiconductor device incorporates a second semiconductor layer with a unique impurity concentration profile, featuring multiple peaks and narrow portions, formed through ion implantation with different acceleration voltages, which suppresses electric field concentration and enhances carrier removal by creating a guard ring structure to prevent breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a diffusion layer is formed in the terminal part to suppress electric field concentration, then breakdown voltage is improved, but carrier removal becomes insufficient leading to avalanche breakdown
Solution Approach 1:
The patent applies local quality by creating a diffusion layer with a specific impurity concentration profile (multiple peaks and narrow portions) in the terminal part, while keeping the cell part structure different. This localized structural differentiation allows the terminal part to simultaneously achieve electric field suppression and improved carrier removal capability through the tailored impurity distribution.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming a diffusion layer with a unique profile featuring multiple peaks and narrow portions. This parameter modification optimizes both the electric field distribution and carrier removal characteristics, resolving the contradiction between breakdown voltage and carrier removal capability.
2Reliability
If the impurity concentration is increased to enhance carrier removal, then avalanche resistance is improved, but electric field concentration increases causing breakdown
Solution Approach 1:
The patent uses local quality by confining the high impurity concentration regions to specific areas (narrow portions) within the diffusion layer, rather than uniformly increasing impurity concentration throughout. This localized approach enhances carrier removal in critical regions while maintaining lower impurity concentrations in other areas to prevent excessive electric field concentration.
Solution Approach 2:
The patent segments the diffusion layer into multiple regions with different impurity concentrations, creating a multi-peaked profile. This segmentation allows different portions of the terminal part to serve different functions: some regions optimized for carrier removal, others for electric field suppression, thereby resolving the contradiction between avalanche resistance and breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses electric field concentration and prevents breakdown in the terminal parts, ensuring reliable operation and maintaining high breakdown voltage performance.
Implementation Method 1
formed through ion implantation with different acceleration voltages
Implementation Method 2
to suppress the concentration of the electric field of the terminal part in the OFF-state and to prevent breakdown of the terminal part
Data Source
AI summary
A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.